Hi Dennis,
Both events are not exactly same. For more details look into intel manual
available on net.
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System
Programming Guide, Part 2
Moreover the event LAST_LEVEL_CACHE_MISSES is an alias as shown by
showeventinfo.
So far as I understand the first two masks are orthogonal to last two masks for
event L2_LINES_IN. That means you can use one of the mask from first two along
with another from last two to get what you want to measure.
Regards,
JK
________________________________
From: Dennis Yang <shinrai...@gmail.com>
To: perfmon2-devel@lists.sourceforge.net
Sent: Wednesday, 11 March, 2009 11:38:20 AM
Subject: [perfmon2] Event info Problem
Hello~
I have run the showevtinfo of perfmon2 on
my Intel Q9550 machine which has 12MB L2 cache.
It shows that it could monitor two hardware
events:
#-----------------------------
Name : L2_LINES_IN
Desc : L2 cache misses
Code : 0x24
Counters : [ 0 1 ]
Umask-00 : 0x40 : [SELF] : This core
Umask-01 : 0xc0 : [BOTH_CORES] : Both cores
Umask-02 : 0x30 : [ANY] : All inclusive
Umask-03 : 0x10 : [PREFETCH] : Hardware prefetch
only
#-----------------------------
Name :
LAST_LEVEL_CACHE_MISSES
Desc : count each
cache miss condition for references to the last level cache. The event count
may include speculation, but excludes cache line fills due to hardware
prefetch. Alias to event L2_RQSTS:SEL
F_DEMAND_I_STATE
Code : 0x412e
Counters : [ 0 1 ]
#-----------------------------
In Q9550, the last level cache is L2 cache.
What is the difference between these two events?
Another question is, does the Umask-01 in
L2_LINES_IN mask the both cores which share the same 6MB L2 cache?
Any help would be grateful!
Dennis
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