Good catch! Historically, AMD has treated the bit field EventSelect<7:5> in model specific register MSRC001_00[03:00] Performance Event Select Register (PERF_CTL[3:0]) like an "event group selector". Please see the "BIOS and Kernel Developer's Guide for AMD Family 10h Processors."
Typically, EventSelect<7:5> == 0x7 selects Northbridge events. Yes, when the event select value was extended to twelve bits, it placed this field somewhere in the middle of the full twelve bit value. ;-) Please consider AMD Family 10h event 0x1C0 Retired x87 Floating Point Operations. This is not a Northbridge event. If the test is greater than or equal to (e.g., 0x1C0 >= 0x0E0), then this event will be incorrectly identified as a Northbridge event. (There are other similar examples.) So, I would recommend testing EventSelect<7:5> == 0x7 in order to detect AMD Northbridge events. Thanks for implementing the AMD event scheduling feature! -- pj Paul Drongowski AMD CodeAnalyst team -----Original Message----- From: stephane eranian [mailto:eran...@googlemail.com] Sent: Wednesday, February 10, 2010 8:58 AM To: Peter Zijlstra Cc: perfmon2-de...@lists.sf.net; fweis...@gmail.com; linux-ker...@vger.kernel.org; Stephane Eranian; pau...@samba.org; mi...@elte.hu; da...@davemloft.net Subject: Re: [perfmon2] [PATCH] perf_events: AMD event scheduling (v3) On Wed, Feb 10, 2010 at 2:28 PM, Peter Zijlstra <pet...@infradead.org> wrote: > On Wed, 2010-02-10 at 14:17 +0100, Peter Zijlstra wrote: >> On Wed, 2010-02-10 at 14:04 +0100, Stephane Eranian wrote: >> >> > > @@ -2268,7 +2268,7 @@ static inline int amd_is_nb_event(struct >> > > u64 val = hwc->config & K7_EVNTSEL_EVENT_MASK; >> > > /* event code : bits [35-32] | [7-0] */ >> > > val = (val >> 24) | (val & 0xff); >> > > - return val >= 0x0e0; >> > > + return val >= 0xe00; >> > > } >> > > >> > I don't understand the change from 0xe0 to 0xe00. >> > That's not the same thing at all. >> > Event select is bits 0-7 + 32-35. >> >> OK that appears to be my bad, because you extended K7_EVNTSEL_EVENT_MASK >> with bit 35 I thought NB events all had bit 35 set. >> >> But looking at the AMD docs it does indeed appear to start at 0xe0, and >> there are no events with bit 35 set, only a few with bit 32. >> >> I'll switch it back to 0xe0. > > Fwiw, for the purpose of that function you might as well write: > > static inline int amd_is_nb_event(struct hw_perf_event *hwc) > { > return (hwc->config & K7_EVNTSEL_EVENT_MASK) > 0xe0; > } > > No need to move bits around higher than the value you compare against. > I think given the existing event codes, that would be fine too. ------------------------------------------------------------------------------ SOLARIS 10 is the OS for Data Centers - provides features such as DTrace, Predictive Self Healing and Award Winning ZFS. Get Solaris 10 NOW http://p.sf.net/sfu/solaris-dev2dev _______________________________________________ perfmon2-devel mailing list perfmon2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/perfmon2-devel ------------------------------------------------------------------------------ SOLARIS 10 is the OS for Data Centers - provides features such as DTrace, Predictive Self Healing and Award Winning ZFS. Get Solaris 10 NOW http://p.sf.net/sfu/solaris-dev2dev _______________________________________________ perfmon2-devel mailing list perfmon2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/perfmon2-devel
