Thanks, that helped!
Currently I am trying to understand how I can count L1 cache misses.
Can I get it simply with MEM_LOAD_RETIRED:L1D_HIT:i:c=1 ?
When do I know if I can use the counter mask or not? In which cases does it
make sense?
2010/11/25 stephane eranian <eran...@googlemail.com>
> Hi,
>
> I think the section of the manual you're referring to talks
> about drill-down on an Intel Core (Core 2) processors. There
> you do have RS_UOPS_DISPATCHED.
>
> If you want to do something similar on Nehalem, I recommend
> you look at the presentations here:
>
>
> https://openlab-mu-internal.web.cern.ch/openlab-mu-internal/00_News/News_pages/2010/10-15_Meeting_David_Levinthal/10-15_Meeting_David_Levinthal.htm
>
> On Thu, Nov 25, 2010 at 4:39 PM, Eduard Diner
> <eduard.di...@googlemail.com> wrote:
> > Hi guys,
> > I have instrumented my code on Nehalem with libpfm4 and now I am a little
> > bit confused.
> > I am reading Intel's "IA64-Optimization-Reference". In Appendix B3.4 they
> > describe a drill-down technique for performance analysis. I think this is
> a
> > good starting point for analysis.
> > Basically I want to map Intel's description in the document to the events
> of
> > libpfm4. This sounds easy... but it is not that easy for me :-)
> >
> >
> > Intel writes for example:
> > "Cycles_non_retiring_uops .... A constant issue rate of μops flowing
> through
> > the issue port. Thus, we define:
> > uops_rate = Dispatch_uops/Cycles_issuing_uops, where Dispatch_uops can be
> > measured with RS_UOPS_DISPATCHED, clearing the INV bit and the CMASK."
> >
> > Well, I don't see a RS_UOPS_DISPATCHED event in libpfm. As far as I
> > understood the architecture, UOPS_DISPATCHED can be expressed as the sum
> of
> > UOPS_RETIRED and UOPS_ISSUED.
> > What do you think?
> >
> > Regards, Eduard
> >
> >
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