Mostly whitespace changes.
Signed-off-by: Robert Richter <robert.rich...@amd.com>
---
lib/amd64_events_fam10h.h | 99 ++++++++++++++++++---------------------------
1 files changed, 40 insertions(+), 59 deletions(-)
diff --git a/lib/amd64_events_fam10h.h b/lib/amd64_events_fam10h.h
index 7cefb24..1d333fe 100644
--- a/lib/amd64_events_fam10h.h
+++ b/lib/amd64_events_fam10h.h
@@ -2008,7 +2008,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
/* 110 */{.pme_name = "READ_REQUEST_TO_L3_CACHE",
.pme_code = 0x4E0,
.pme_desc = "Read Request to L3 Cache",
- .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_TILL_FAM10H_REV_C,
+ .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_TILL_FAM10H_REV_C,
.pme_numasks = 5,
.pme_umasks = {
{ .pme_uname = "READ_BLOCK_EXCLUSIVE",
@@ -2060,7 +2060,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
/* 111 */{.pme_name = "L3_CACHE_MISSES",
.pme_code = 0x4E1,
.pme_desc = "L3 Cache Misses",
- .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_TILL_FAM10H_REV_C,
+ .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_TILL_FAM10H_REV_C,
.pme_numasks = 5,
.pme_umasks = {
{ .pme_uname = "READ_BLOCK_EXCLUSIVE",
@@ -2112,7 +2112,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
/* 112 */{.pme_name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS",
.pme_code = 0x4E2,
.pme_desc = "L3 Fills caused by L2 Evictions",
- .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_TILL_FAM10H_REV_C,
+ .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_TILL_FAM10H_REV_C,
.pme_numasks = 6,
.pme_umasks = {
{ .pme_uname = "SHARED",
@@ -2133,7 +2133,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
},
{ .pme_uname = "ANY_STATE",
.pme_udesc = "any line state (shared, owned, exclusive,
modified)",
- .pme_ucode = 0x0f,
+ .pme_ucode = 0x0F,
},
#if 0
/*
@@ -2199,7 +2199,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
/* 114 */{.pme_name = "PAGE_SIZE_MISMATCHES",
.pme_code = 0x165,
.pme_desc = "Page Size Mismatches",
- .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_FAM10H_REV_C,
+ .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_FAM10H_REV_C,
.pme_numasks = 4,
.pme_umasks = {
{ .pme_uname = "GUEST_LARGER",
@@ -2223,7 +2223,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
/* 115 */{.pme_name = "RETIRED_X87_OPS",
.pme_code = 0x1C0,
.pme_desc = "Retired x87 Floating Point Operations",
- .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_FAM10H_REV_C,
+ .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_FAM10H_REV_C,
.pme_numasks = 4,
.pme_umasks = {
{ .pme_uname = "ADD_SUB_OPS",
@@ -2270,7 +2270,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
/* 120 */{.pme_name = "READ_REQUEST_TO_L3_CACHE",
.pme_code = 0x4E0,
.pme_desc = "Read Request to L3 Cache",
- .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_FAM10H_REV_D,
+ .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_FAM10H_REV_D,
.pme_numasks = 5,
.pme_umasks = {
{ .pme_uname = "READ_BLOCK_EXCLUSIVE",
@@ -2335,7 +2335,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
/* 121 */{.pme_name = "L3_CACHE_MISSES",
.pme_code = 0x4E1,
.pme_desc = "L3 Cache Misses",
- .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_FAM10H_REV_D,
+ .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_FAM10H_REV_D,
.pme_numasks = 5,
.pme_umasks = {
{ .pme_uname = "READ_BLOCK_EXCLUSIVE",
@@ -2400,7 +2400,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
/* 122 */{.pme_name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS",
.pme_code = 0x4E2,
.pme_desc = "L3 Fills caused by L2 Evictions",
- .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_FAM10H_REV_D,
+ .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_FAM10H_REV_D,
.pme_numasks = 6,
.pme_umasks = {
{ .pme_uname = "SHARED",
@@ -2421,7 +2421,7 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
},
{ .pme_uname = "ANY_STATE",
.pme_udesc = "any line state (shared, owned, exclusive,
modified)",
- .pme_ucode = 0x0f,
+ .pme_ucode = 0x0F,
},
#if 0
/*
@@ -2467,36 +2467,37 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
},
},
/* 123 */{.pme_name = "IBSOP_EVENT",
- .pme_code = 0xFF,
- .pme_desc = "Enable IBS OP mode (pseudo event)",
- .pme_flags = 0,
- .pme_numasks = 2,
- .pme_umasks = {
- { .pme_uname = "CYCLES",
- .pme_udesc = "sample cycles",
- .pme_ucode = 0x01,
- },
- { .pme_uname = "UOPS",
- .pme_udesc = "sample dispatched uops (Rev C and later)",
- .pme_ucode = 0x02,
- },
- },
- },
+ .pme_code = 0xFF,
+ .pme_desc = "Enable IBS OP mode (pseudo event)",
+ .pme_flags = 0,
+ .pme_numasks = 2,
+ .pme_umasks = {
+ { .pme_uname = "CYCLES",
+ .pme_udesc = "sample cycles",
+ .pme_ucode = 0x01,
+ },
+ { .pme_uname = "UOPS",
+ .pme_udesc = "sample dispatched uops (Rev C and later)",
+ .pme_ucode = 0x02,
+ },
+ },
+ },
/* 124 */{.pme_name = "IBSFETCH_EVENT",
- .pme_code = 0xFF,
- .pme_desc = "Enable IBS Fetch mode (pseudo event)",
- .pme_flags = 0,
- .pme_numasks = 2,
- .pme_umasks = {
- { .pme_uname = "RANDOM",
- .pme_udesc = "randomize period",
- .pme_ucode = 0x01,
- },
- { .pme_uname = "NO_RANDOM",
- .pme_udesc = "do not randomize period",
- }
- },
- },
+ .pme_code = 0xFF,
+ .pme_desc = "Enable IBS Fetch mode (pseudo event)",
+ .pme_flags = 0,
+ .pme_numasks = 2,
+ .pme_umasks = {
+ { .pme_uname = "RANDOM",
+ .pme_udesc = "randomize period",
+ .pme_ucode = 0x01,
+ },
+ { .pme_uname = "NO_RANDOM",
+ .pme_udesc = "do not randomize period",
+ .pme_ucode = 0x00,
+ },
+ },
+ },
/* 125 */{.pme_name = "MAB_REQUESTS",
.pme_code = 0x68,
.pme_desc = "Average L1 refill latency for Icache and Dcache misses
(request count for cache refills)",
@@ -2505,52 +2506,42 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
{ .pme_uname = "BUFFER_0",
.pme_udesc = "Buffer 0",
.pme_ucode = 0x00,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_1",
.pme_udesc = "Buffer 1",
.pme_ucode = 0x01,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_2",
.pme_udesc = "Buffer 2",
.pme_ucode = 0x02,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_3",
.pme_udesc = "Buffer 3",
.pme_ucode = 0x03,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_4",
.pme_udesc = "Buffer 4",
.pme_ucode = 0x04,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_5",
.pme_udesc = "Buffer 5",
.pme_ucode = 0x05,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_6",
.pme_udesc = "Buffer 6",
.pme_ucode = 0x06,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_7",
.pme_udesc = "Buffer 7",
.pme_ucode = 0x07,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_8",
.pme_udesc = "Buffer 8",
.pme_ucode = 0x08,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_9",
.pme_udesc = "Buffer 9",
.pme_ucode = 0x09,
- .pme_uflags = 0,
},
},
},
@@ -2562,52 +2553,42 @@ static pme_amd64_entry_t amd64_fam10h_pe[]={
{ .pme_uname = "BUFFER_0",
.pme_udesc = "Buffer 0",
.pme_ucode = 0x00,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_1",
.pme_udesc = "Buffer 1",
.pme_ucode = 0x01,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_2",
.pme_udesc = "Buffer 2",
.pme_ucode = 0x02,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_3",
.pme_udesc = "Buffer 3",
.pme_ucode = 0x03,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_4",
.pme_udesc = "Buffer 4",
.pme_ucode = 0x04,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_5",
.pme_udesc = "Buffer 5",
.pme_ucode = 0x05,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_6",
.pme_udesc = "Buffer 6",
.pme_ucode = 0x06,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_7",
.pme_udesc = "Buffer 7",
.pme_ucode = 0x07,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_8",
.pme_udesc = "Buffer 8",
.pme_ucode = 0x08,
- .pme_uflags = 0,
},
{ .pme_uname = "BUFFER_9",
.pme_udesc = "Buffer 9",
.pme_ucode = 0x09,
- .pme_uflags = 0,
},
},
},
--
1.7.3.4
------------------------------------------------------------------------------
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