For Intel Nehalem and later, you want to use the OFFCORE_RESPONSE event.
It does allow you do filter based on memory request and response and
that includes
prefetches.


On Wed, Oct 10, 2012 at 6:43 PM, Leonardo Piga <leonardo.p...@gmail.com> wrote:
> For AMDs there are northbridge counters but they are per tile (group of 
> cores).
>
>
> Leonardo
>
>
> On Wed, Oct 10, 2012 at 1:41 PM, Yuanfang Chen <tabloid.adr...@gmail.com> 
> wrote:
>> On Wed, Oct 10, 2012 at 12:30 PM, heechul Yun <heec...@illinois.edu> wrote:
>>> Hello
>>>
>>> I am looking for a way to accurately accounting memory traffic generated
>>> from each core in recent intel architecture.
>>> I tried LLC miss counter to calculate the memory traffic of each core, but
>>> it doesn't include prefetched traffic.
>>> Is there any performance counter that accounts both LLC miss and h/w
>>> prefetcher induced memory traffic?
>>
>> That's architecture dependent. For intel snb, these metrics can be
>> customized using offcore events. Details can be found in intel sdm
>> vol3, chapter 18,19.
>>
>> yuanfang
>>
>>
>>>
>>> Best,
>>>
>>> Heechul
>>>
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