Hi Will,
after a long time I looked into this again:
On 2018-01-10 20:43, William Cohen wrote:
> For the sparc processors it looks like the same event number measures a
> different event depending on what register it is programmed into. Looking
> through sparc documentation the dispatch0_2n_br looks like it should be
> register 0, so expect that the Dispatch0_rs_mispred should be register 1.
> The other attached patch should address the problem, but has not been tested
> and should have someone verify that it is correct.
>> sparc64:
>> =======
>>
>> ./tests/validate
>> Libpfm structure tests:
>> libpfm ABI version : 0
>> pfm_pmu_info_t : Passed
>> pfm_event_info_t : Passed
>> pfm_event_attr_info_t : Passed
>> pfm_pmu_encode_arg_t : Passed
>> pfm_perf_encode_arg_t : Passed
>> Libpfm internal table tests:
>> checking ultra12 (22 events): Passed
>> checking ultra3 (65 events): pmu: ultra3 event12: Dispatch0_2nd_br
>> code: 0x4 is duplicated in event24 : Dispatch0_rs_mispred
>> Failed
>> checking ultra3i (63 events): pmu: ultra3i event12: Dispatch0_2nd_br
>> code: 0x4 is duplicated in event24 : Dispatch0_rs_mispred
>> Failed
>> checking ultra3p (71 events): pmu: ultra3p event12: Dispatch0_2nd_br
>> code: 0x4 is duplicated in event24 : Dispatch0_rs_mispred
>> Failed
>> checking ultra4p (103 events): Passed
>> checking niagara1 (9 events): Passed
>> checking niagara2 (8 events): Passed
>> checking perf (80 events): Passed
>> checking perf_raw (1 events): Passed
>> Architecture specific tests:
>> Total 3 errors
That patch for sparc did not help.
But it looks like there are three events using .code = 0x4, while there
are only two registers available to distinguish them - so this cannot
work.
$ grep '.code =' lib/events/sparc* | sort | uniq -c | sort -n
[...]
3 lib/events/sparc_ultra3i_events.h: .code = 0x4,
3 lib/events/sparc_ultra3plus_events.h: .code = 0x4,
lib/events/sparc_ultra3i_events.h:
[...]
/* PIC0 events common to all UltraSPARC-III/III+/IIIi processors */
[...]
{
.name = "Dispatch0_2nd_br",
.desc = "Stall cycles due...",
.ctrl = PME_CTRL_S0,
.code = 0x4,
},
[...]
{
.name = "Dispatch0_rs_mispred",
.desc = "I-buffer is empty...",
.ctrl = PME_CTRL_S0,
.code = 0x4,
},
[...]
/* PIC1 events specific to UltraSPARC-III+/IIIi */
{
.name = "Re_DC_missovhd",
.desc = "Used to measure D-cache...",
.ctrl = PME_CTRL_S1,
.code = 0x4,
},
[...]
The Dispatch0_rs_mispred event also appears to be placed out of order in
the otherwise segment-wise sorted list ... 0x4 between 0x16 and 0x18.
Andreas
_______________________________________________
perfmon2-devel mailing list
perfmon2-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/perfmon2-devel
