On Power5, the time-base (TB) register is read-only, so indicate that in the
PMD table. Also, add the PURR register to the table, which is also read-only.
Signed-off-by: Kevin Corry <[EMAIL PROTECTED]>
Signed-off-by: Carl Love <[EMAIL PROTECTED]>
Index: linux-2.6.20-arnd3-perfmon4/arch/powerpc/perfmon/perfmon_power5.c
===================================================================
--- linux-2.6.20-arnd3-perfmon4.orig/arch/powerpc/perfmon/perfmon_power5.c
+++ linux-2.6.20-arnd3-perfmon4/arch/powerpc/perfmon/perfmon_power5.c
@@ -36,14 +36,19 @@ static struct pfm_reg_desc pfm_power5_pm
};
#define PFM_PM_NUM_PMCS ARRAY_SIZE(pfm_power5_pmc_desc)
+/* The TB and PURR registers are read-only. Also, note that the TB register
+ * actually consists of both the 32-bit SPRN_TBRU and SPRN_TBRL registers.
+ * For Perfmon2's purposes, we'll treat it as a single 64-bit register.
+ */
static struct pfm_reg_desc pfm_power5_pmd_desc[]={
-/* tb */ PMD_D(PFM_REG_C, "TB" , SPRN_TBRL),
+/* tb */ PMD_D((PFM_REG_I|PFM_REG_RO), "TB", SPRN_TBRL),
/* pmd1 */ PMD_D(PFM_REG_C, "PMC1", SPRN_PMC1),
/* pmd2 */ PMD_D(PFM_REG_C, "PMC2", SPRN_PMC2),
/* pmd3 */ PMD_D(PFM_REG_C, "PMC3", SPRN_PMC3),
/* pmd4 */ PMD_D(PFM_REG_C, "PMC4", SPRN_PMC4),
/* pmd5 */ PMD_D(PFM_REG_C, "PMC5", SPRN_PMC5),
/* pmd6 */ PMD_D(PFM_REG_C, "PMC6", SPRN_PMC6),
+/* purr */ PMD_D((PFM_REG_I|PFM_REG_RO), "PURR", SPRN_PURR),
};
#define PFM_PM_NUM_PMDS ARRAY_SIZE(pfm_power5_pmd_desc)
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