Kevin, On Mon, May 21, 2007 at 09:24:19AM -0500, Kevin Corry wrote: > > Here are some short fixes/cleanups for perfmon's powerpc architecture code. > I'll also start sending in a batch of patches soon with the Cell support that > we've been working on. > Applied all patches.
Thanks for your contributions. > 1/5 > Add the hardware addresses to the register descriptions for the power5 pmu. > > 2/5 > On Power5, the time-base (TB) register is read-only, so indicate that in the > PMD table. Also, add the PURR register to the table, which is also read-only. > > 3/5 > Rename the ppc32_pmu_type enum to powerpc_pmu_type, since we'll be using that > with all of the powerpc models. Also rename the enum values to better match > the naming scheme used in i386 and x86-64. > > 4/5 > Add a pfm_arch_pmu_info structure for the POWER5 module. Each powerpc model > will need one of these so we can differentiate in the pfm_arch_* routines. > > 5/5 > The pfm_arch_unfreeze_pmu() routine is never called. Use > pfm_arch_intr_unfreeze_pmu() instead. > > Thanks, -- -Stephane _______________________________________________ perfmon mailing list [email protected] http://www.hpl.hp.com/hosted/linux/mail-archives/perfmon/
