Kevin, I have to take exception to your comments about
interrupt sharing.
There is nothing wrong with sharing interrupts and handler
chaining per se. I have been programming embedded software
using shared interrupts for many years without any negative
effects. It does add extra time to service an interrupt,
but if you cater for this in the performance requirements
then it is simply not a problem.
However the original PC ISA bus specified edge triggered
interrupts which is entirely not compatible with the idea
of interrupt sharing. Also when the XT was expanded to the
AT, the additional second PIC slaved to IRQ 2 totally
screwed the IRQ priority ordering, we have still not
recovered from that to this day.
To implement PCI on the AT architecture forces interrupt
sharing due to the limited available interrupts. The PCI
spec provides level triggered interrupts thus allowing
sharing to actually work with correctly written drivers.
I don't believe that the intent of the PCI spec was to
force a shared IRQ architecture, it simply allows for it
if required. The spec goes into details on sharing because
the reality of the situation was that PCI (an Intel
initiative) would first be implemented on AT architecture
machines using Intel chips.
There is nothing stopping all interrupt pins on all PCI
slots being given a unique IRQ in a custom interrupt
controller. The very idea of making 4 interrupt lines
available per slot was to allow multiple functions in a
slot to have a unique IRQ and thus _prevent_ sharing. MP
motherboards using an APIC with extended IRQs will allow
the OS to remap PCI device to IRQs greater than 15 so they
are no longer shared.
It might be worth emulating an APIC in Plex86, even before
we have multiple CPUs emulated in independant threads. :-)
FreeBSD, Linux and Windows 2000 (that I know of) will make
use of the extended IRQs and speed up IRQ emulation by not
chaining IRQ handlers.
> FWIW, the PCI idea is pretty cool. Though it was a real big mistake
> to include interrupt lines (those A,B,C,D lines) as part of the
> spec. What a mess. When I was reading a PCI book, I thought
> hey this is a pretty cool architecture until I got to the part
> where they talked about interrupt lines. WTF? Interrupt
> handler chaining - did we learn nothing from the past? Then they
> explain that a newer mechanism was added which doesn't require
> these. But of course, then you have both mechanisms. This
> is too familiar to me.
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