On Tuesday 24 July 2001 14:55, you wrote:
> Drew Northup wrote:
> > I was reading some about PCI last night, and have a question. Is the
> > CPU a PCI client like everything else, or not?
>
> The North Bridge resides on multiple buses. For example, it
> sits on the processor (host) bus. There are unique electrical
> signalings there and different requirements than on the PCI bus.
> Ideally you could design a NB to handle various processor types
> so you don't want to require processors to be "PCI devices".
>
> Also sits on the memory bus. Here you optimize the bus for
> memory transfers. Ideally you could develop a NB based on
> various memory types, so you don't want a memory requirement
> of being a "PCI device" either.
>
> And of course, the NB is on the PCI bus. On this bus, the
> devices have to comply with the PCI spec. They respond to
> PCI protocol.
>
> The AGP bus is implemented creatively on at least the i440BX.
> It's implemented as another "logical" PCI bus, but within the
> NB.
>
> -Kevin
The Northbridge includes a CPU bus to PCI bus bridge. This is a PCI device
just like any other to the other PCI devices (thought the bus it resides on
is numbered "0"). The CPU memory is typically mapped into PCI bus address
space with the same address as the physical address on the CPU bus, so though
the two addresses are conceptually different, they have identical numerical
values (which makes DMA *much* simpler). This doesn't matter at all if the
other PCI devices are all pure slave devices, but if they are bus mastering,
they can write directly into host memory without any hardware intervention on
the host side (even the CPU need not be involved at all, although CPU
moderated setup is usually a good idea!), unlike ISA DMA, which requires a
DMA controller on the MB.
The above is written without reference to docs., but I doubt its too far off
base, as I'm actually writting DMA drivers for a PCI card at the moment.
Colin
