Hi all,
I've been following this thread and the one about chipsets with much
interest, and I might have something to contribute. I've no idea how
plex86 works internally, but I believe I do something very similar in my
own job. I am an ASIC designer (see www.clearspeed.com) and I write C++
code that models a chip that forms part of a network router.
For the application code that runs on this router chip (akin to the
plex86 guest OS) , the C++ model of the chip must look just like the
real hardware, but the internal architecture of the C++ model can be
very different from the real hardware. This allows much higher levels of
abstraction to be used in the model, and hence it runs faster.
There seems to be a lot of discussion about making plex86 accurately
model the PC architecture, including ISA, PCI, AGP, chipsets etc. My
question is is this really necessary? For example, why bother providing
AGP support in plex86? Just because it's faster in a real PC does not
mean it'll be faster in plex86. Don't forget that you might be able to
'cheat', since you are not constrained by clock speeds, bus contention
etc. Another example, a real hardware bus is a shared resource, but a
modelled bus can be implemented as a large crossbar switch that never
has contention.
I apologise if this is already obvious to the developers. I really ought
to have a look at the plex86 source myself!
Regards,
Jeff
