Dear suhas hv,
On 18.9.2020 8.50, suhas hv wrote:
I would like to run the example fixed function accelerator. I am
following the instructions under the section "System-on-a-chip design
with AlmaIF Integrator" in the TCE user manual. However I am not able to
execute the very first step of generating the processor. I am unable to
build TCE on my computer even though I am following the instructions
given. The error is to do with LLVM and I'm not sure of how to resolve it.
TCE is an independent project from PoCL, thus the problems related to
its build thus belong to its github or mailing list available via
http://openasip.org.
Anyways: "Problems with LLVM and TCE" usually are related to getting the
system in the way with the TCE-patched LLVM. Ensure this doesn't happen
via proper environment variables and it likely fixes your issues (I've
seen this multiple times).
I am unsure as to whether this first step of generating the processor is
necessary since the VHDL code of the accelerator is already present in
the POCL github repository. I have tried to include the RTL
Not necessary, that's why we included the RTL of the example
accelerator to avoid the need to install TCE. You should be able to skip
the ASIP generation and start from 3.12.3.
Can the steps involved in running the example fixed function accelerator
kindly be shared with me?
The steps are there. We tested them with another student (than who
wrote the manual steps) in our group independently and he was able to
reproduce the accelerator execution with these steps. If you have
challenges with Vivado, those questions belong to Xilinx tool support
channels.
BR,
--
Pekka
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