Merge in bits from base.. - Merge LLVM commits r340844, r353818 and r353819 from the 8.0 branch to fix a regression in floating point operations. - When generating code for OpenBSD/powerpc, avoid unaligned floating-point load and store instructions. - Skip retguard instructions in prologue detection. - When bsd.lib.mk builds shared libraries it builds with -DPIC which causes problems in the following files which use PIC as a variable name.
Index: Makefile =================================================================== RCS file: /home/cvs/ports/devel/llvm/Makefile,v retrieving revision 1.212 diff -u -p -u -p -r1.212 Makefile --- Makefile 11 Feb 2019 05:33:57 -0000 1.212 +++ Makefile 18 Feb 2019 19:33:06 -0000 @@ -20,7 +20,8 @@ PKGSPEC-main = llvm-=${LLVM_V} PKGNAME-main = llvm-${LLVM_V} PKGNAME-python = py-llvm-${LLVM_V} PKGNAME-lldb = lldb-${LLVM_V} -REVISION-main = 5 +REVISION-main = 6 +REVISION-lldb = 0 CATEGORIES = devel DISTFILES = llvm-${LLVM_V}.src${EXTRACT_SUFX} \ cfe-${LLVM_V}.src${EXTRACT_SUFX} \ Index: patches/patch-include_llvm_Config_llvm-config_h_cmake =================================================================== RCS file: patches/patch-include_llvm_Config_llvm-config_h_cmake diff -N patches/patch-include_llvm_Config_llvm-config_h_cmake --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-include_llvm_Config_llvm-config_h_cmake 18 Feb 2019 19:19:28 -0000 @@ -0,0 +1,28 @@ +$OpenBSD$ + +When bsd.lib.mk builds shared libraries it builds with -DPIC which +causes problems in the following files which use PIC as a variable name. +Undefine PIC in llvm-config.h to minimise the diff to upstream LLVM. + +Index: include/llvm/Config/llvm-config.h.cmake +--- include/llvm/Config/llvm-config.h.cmake.orig ++++ include/llvm/Config/llvm-config.h.cmake +@@ -14,6 +14,18 @@ + #ifndef LLVM_CONFIG_H + #define LLVM_CONFIG_H + ++/* ++ * When bsd.lib.mk builds shared libraries it builds with -DPIC which ++ * causes problems in the following files which use PIC as a variable name. ++ * undefine PIC here to minimise the diff to upstream LLVM ++ * ++ * include/llvm/MC/MCObjectFileInfo.h ++ * lib/MC/MCObjectFileInfo.cpp ++ * lib/Transforms/Scalar/LICM.cpp ++ * lib/Transforms/Utils/PredicateInfo.cpp ++ */ ++#undef PIC ++ + /* Define if LLVM_ENABLE_DUMP is enabled */ + #cmakedefine LLVM_ENABLE_DUMP + Index: patches/patch-lib_Target_PowerPC_PPCISelLowering_cpp =================================================================== RCS file: patches/patch-lib_Target_PowerPC_PPCISelLowering_cpp diff -N patches/patch-lib_Target_PowerPC_PPCISelLowering_cpp --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-lib_Target_PowerPC_PPCISelLowering_cpp 18 Feb 2019 19:47:58 -0000 @@ -0,0 +1,27 @@ +$OpenBSD$ + +When generating code for OpenBSD/powerpc, avoid unaligned floating-point +load and store instructions. The vast majority of PowerPC CPUs that +OpenBSD runs on don't implement those and will generate an alignment +exceptions. While we do emulate lfd and stfd (to work around GCC bugs), +we don't emulate lfs and stfs. It is way more efficient to have the +compiler generate code that only uses aligned load and store instructions. + +Index: lib/Target/PowerPC/PPCISelLowering.cpp +--- lib/Target/PowerPC/PPCISelLowering.cpp.orig ++++ lib/Target/PowerPC/PPCISelLowering.cpp +@@ -13921,6 +13921,14 @@ bool PPCTargetLowering::allowsMisalignedMemoryAccesses + if (VT == MVT::ppcf128) + return false; + ++ if (Subtarget.isTargetOpenBSD()) { ++ // Traditional PowerPC does not support unaligned memory access ++ // for floating-point and the OpenBSD kernel does not emulate ++ // all possible floating-point load-store instructions. ++ if (VT == MVT::f32 || VT == MVT::f64) ++ return false; ++ } ++ + if (Fast) + *Fast = true; + Index: patches/patch-lib_Target_PowerPC_PPCSubtarget_h =================================================================== RCS file: patches/patch-lib_Target_PowerPC_PPCSubtarget_h diff -N patches/patch-lib_Target_PowerPC_PPCSubtarget_h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-lib_Target_PowerPC_PPCSubtarget_h 18 Feb 2019 19:48:14 -0000 @@ -0,0 +1,20 @@ +$OpenBSD$ + +When generating code for OpenBSD/powerpc, avoid unaligned floating-point +load and store instructions. The vast majority of PowerPC CPUs that +OpenBSD runs on don't implement those and will generate an alignment +exceptions. While we do emulate lfd and stfd (to work around GCC bugs), +we don't emulate lfs and stfs. It is way more efficient to have the +compiler generate code that only uses aligned load and store instructions. + +Index: lib/Target/PowerPC/PPCSubtarget.h +--- lib/Target/PowerPC/PPCSubtarget.h.orig ++++ lib/Target/PowerPC/PPCSubtarget.h +@@ -305,6 +305,7 @@ class PPCSubtarget : public PPCGenSubtargetInfo { (pub + bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } + bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } + bool isTargetLinux() const { return TargetTriple.isOSLinux(); } ++ bool isTargetOpenBSD() const { return TargetTriple.isOSOpenBSD(); } + + bool isDarwinABI() const { return isTargetMachO() || isDarwin(); } + bool isSVR4ABI() const { return !isDarwinABI(); } Index: patches/patch-lib_Target_X86_AsmParser_X86AsmParser_cpp =================================================================== RCS file: patches/patch-lib_Target_X86_AsmParser_X86AsmParser_cpp diff -N patches/patch-lib_Target_X86_AsmParser_X86AsmParser_cpp --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-lib_Target_X86_AsmParser_X86AsmParser_cpp 18 Feb 2019 19:09:01 -0000 @@ -0,0 +1,18 @@ +$OpenBSD$ + +Merge LLVM commits r340844, r353818 and r353819 from the 8.0 branch +to fix a regression in floating point operations. + +Index: lib/Target/X86/AsmParser/X86AsmParser.cpp +--- lib/Target/X86/AsmParser/X86AsmParser.cpp.orig ++++ lib/Target/X86/AsmParser/X86AsmParser.cpp +@@ -1109,8 +1109,7 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo, + } + + // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens. +- if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) { +- RegNo = X86::ST0; ++ if (RegNo == X86::ST0) { + Parser.Lex(); // Eat 'st' + + // Check to see if we have '(4)' after %st. Index: patches/patch-lib_Target_X86_InstPrinter_X86ATTInstPrinter_cpp =================================================================== RCS file: patches/patch-lib_Target_X86_InstPrinter_X86ATTInstPrinter_cpp diff -N patches/patch-lib_Target_X86_InstPrinter_X86ATTInstPrinter_cpp --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-lib_Target_X86_InstPrinter_X86ATTInstPrinter_cpp 18 Feb 2019 19:14:01 -0000 @@ -0,0 +1,23 @@ +$OpenBSD$ + +Merge LLVM commits r340844, r353818 and r353819 from the 8.0 branch +to fix a regression in floating point operations. + +Index: lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp +--- lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp.orig ++++ lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp +@@ -200,3 +200,14 @@ void X86ATTInstPrinter::printU8Imm(const MCInst *MI, u + O << markup("<imm:") << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff) + << markup(">"); + } ++ ++void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo, ++ raw_ostream &OS) { ++ const MCOperand &Op = MI->getOperand(OpNo); ++ unsigned Reg = Op.getReg(); ++ // Override the default printing to print st(0) instead st. ++ if (Reg == X86::ST0) ++ OS << markup("<reg:") << "%st(0)" << markup(">"); ++ else ++ printRegName(OS, Reg); ++} Index: patches/patch-lib_Target_X86_InstPrinter_X86ATTInstPrinter_h =================================================================== RCS file: patches/patch-lib_Target_X86_InstPrinter_X86ATTInstPrinter_h diff -N patches/patch-lib_Target_X86_InstPrinter_X86ATTInstPrinter_h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-lib_Target_X86_InstPrinter_X86ATTInstPrinter_h 18 Feb 2019 19:13:57 -0000 @@ -0,0 +1,16 @@ +$OpenBSD$ + +Merge LLVM commits r340844, r353818 and r353819 from the 8.0 branch +to fix a regression in floating point operations. + +Index: lib/Target/X86/InstPrinter/X86ATTInstPrinter.h +--- lib/Target/X86/InstPrinter/X86ATTInstPrinter.h.orig ++++ lib/Target/X86/InstPrinter/X86ATTInstPrinter.h +@@ -44,6 +44,7 @@ class X86ATTInstPrinter final : public X86InstPrinterC + void printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O); + void printDstIdx(const MCInst *MI, unsigned Op, raw_ostream &O); + void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &OS); ++ void printSTiRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS); + + void printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); Index: patches/patch-lib_Target_X86_InstPrinter_X86IntelInstPrinter_cpp =================================================================== RCS file: patches/patch-lib_Target_X86_InstPrinter_X86IntelInstPrinter_cpp diff -N patches/patch-lib_Target_X86_InstPrinter_X86IntelInstPrinter_cpp --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-lib_Target_X86_InstPrinter_X86IntelInstPrinter_cpp 18 Feb 2019 19:14:28 -0000 @@ -0,0 +1,23 @@ +$OpenBSD$ + +Merge LLVM commits r340844, r353818 and r353819 from the 8.0 branch +to fix a regression in floating point operations. + +Index: lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp +--- lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp.orig ++++ lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp +@@ -160,3 +160,14 @@ void X86IntelInstPrinter::printU8Imm(const MCInst *MI, + + O << formatImm(MI->getOperand(Op).getImm() & 0xff); + } ++ ++void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo, ++ raw_ostream &OS) { ++ const MCOperand &Op = MI->getOperand(OpNo); ++ unsigned Reg = Op.getReg(); ++ // Override the default printing to print st(0) instead st. ++ if (Reg == X86::ST0) ++ OS << "st(0)"; ++ else ++ printRegName(OS, Reg); ++} Index: patches/patch-lib_Target_X86_InstPrinter_X86IntelInstPrinter_h =================================================================== RCS file: patches/patch-lib_Target_X86_InstPrinter_X86IntelInstPrinter_h diff -N patches/patch-lib_Target_X86_InstPrinter_X86IntelInstPrinter_h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-lib_Target_X86_InstPrinter_X86IntelInstPrinter_h 18 Feb 2019 19:14:33 -0000 @@ -0,0 +1,16 @@ +$OpenBSD$ + +Merge LLVM commits r340844, r353818 and r353819 from the 8.0 branch +to fix a regression in floating point operations. + +Index: lib/Target/X86/InstPrinter/X86IntelInstPrinter.h +--- lib/Target/X86/InstPrinter/X86IntelInstPrinter.h.orig ++++ lib/Target/X86/InstPrinter/X86IntelInstPrinter.h +@@ -39,6 +39,7 @@ class X86IntelInstPrinter final : public X86InstPrinte + void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O); ++ void printSTiRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS); + + void printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); Index: patches/patch-lib_Target_X86_X86ISelLowering_cpp =================================================================== RCS file: patches/patch-lib_Target_X86_X86ISelLowering_cpp diff -N patches/patch-lib_Target_X86_X86ISelLowering_cpp --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-lib_Target_X86_X86ISelLowering_cpp 18 Feb 2019 19:04:53 -0000 @@ -0,0 +1,29 @@ +$OpenBSD$ + +Merge LLVM commits r340844, r353818 and r353819 from the 8.0 branch +to fix a regression in floating point operations. + +Index: lib/Target/X86/X86ISelLowering.cpp +--- lib/Target/X86/X86ISelLowering.cpp.orig ++++ lib/Target/X86/X86ISelLowering.cpp +@@ -40619,6 +40619,20 @@ X86TargetLowering::getRegForInlineAsmConstraint(const + return Res; + } + ++ // dirflag -> DF ++ if (StringRef("{dirflag}").equals_lower(Constraint)) { ++ Res.first = X86::DF; ++ Res.second = &X86::DFCCRRegClass; ++ return Res; ++ } ++ ++ // fpsr -> FPSW ++ if (StringRef("{fpsr}").equals_lower(Constraint)) { ++ Res.first = X86::FPSW; ++ Res.second = &X86::FPCCRRegClass; ++ return Res; ++ } ++ + // 'A' means [ER]AX + [ER]DX. + if (Constraint == "A") { + if (Subtarget.is64Bit()) { Index: patches/patch-lib_Target_X86_X86InstrFPStack_td =================================================================== RCS file: patches/patch-lib_Target_X86_X86InstrFPStack_td diff -N patches/patch-lib_Target_X86_X86InstrFPStack_td --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-lib_Target_X86_X86InstrFPStack_td 18 Feb 2019 19:05:31 -0000 @@ -0,0 +1,300 @@ +$OpenBSD$ + +Merge LLVM commits r340844, r353818 and r353819 from the 8.0 branch +to fix a regression in floating point operations. + +Index: lib/Target/X86/X86InstrFPStack.td +--- lib/Target/X86/X86InstrFPStack.td.orig ++++ lib/Target/X86/X86InstrFPStack.td +@@ -230,7 +230,7 @@ def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), + } // mayLoad = 1, hasSideEffects = 1 + } + +-let Defs = [FPSW] in { ++let Defs = [FPSW], Uses = [FPCW] in { + // FPBinary_rr just defines pseudo-instructions, no need to set a scheduling + // resources. + let hasNoSchedulingInfo = 1 in { +@@ -258,42 +258,42 @@ defm DIVR: FPBinary<fdiv, MRM7m, "divr", 0>; + } // Defs = [FPSW] + + class FPST0rInst<Format fp, string asm> +- : FPI<0xD8, fp, (outs), (ins RST:$op), asm>; ++ : FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>; + class FPrST0Inst<Format fp, string asm> +- : FPI<0xDC, fp, (outs), (ins RST:$op), asm>; ++ : FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>; + class FPrST0PInst<Format fp, string asm> +- : FPI<0xDE, fp, (outs), (ins RST:$op), asm>; ++ : FPI<0xDE, fp, (outs), (ins RSTi:$op), asm>; + + // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion + // of some of the 'reverse' forms of the fsub and fdiv instructions. As such, + // we have to put some 'r's in and take them out of weird places. +-let SchedRW = [WriteFAdd] in { +-def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t$op">; +-def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st(0), $op|$op, st(0)}">; +-def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t$op">; +-def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t$op">; +-def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st(0), $op|$op, st(0)}">; +-def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t$op">; +-def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t$op">; +-def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st(0), $op|$op, st(0)}">; +-def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t$op">; ++let SchedRW = [WriteFAdd], Defs = [FPSW], Uses = [FPCW] in { ++def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">; ++def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">; ++def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">; ++def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">; ++def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">; ++def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">; ++def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">; ++def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">; ++def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">; + } // SchedRW +-let SchedRW = [WriteFCom] in { ++let SchedRW = [WriteFCom], Defs = [FPSW], Uses = [FPCW] in { + def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; + def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; + } // SchedRW +-let SchedRW = [WriteFMul] in { +-def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">; +-def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st(0), $op|$op, st(0)}">; +-def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t$op">; ++let SchedRW = [WriteFMul], Defs = [FPSW], Uses = [FPCW] in { ++def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">; ++def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">; ++def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">; + } // SchedRW +-let SchedRW = [WriteFDiv] in { +-def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t$op">; +-def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st(0), $op|$op, st(0)}">; +-def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t$op">; +-def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t$op">; +-def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">; +-def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">; ++let SchedRW = [WriteFDiv], Defs = [FPSW], Uses = [FPCW] in { ++def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">; ++def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">; ++def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">; ++def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t{$op, %st|st, $op}">; ++def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">; ++def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t{%st, $op|$op, st}">; + } // SchedRW + + // Unary operations. +@@ -307,7 +307,7 @@ def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), + def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; + } + +-let Defs = [FPSW] in { ++let Defs = [FPSW], Uses = [FPCW] in { + + let SchedRW = [WriteFSign] in { + defm CHS : FPUnary<fneg, MRM_E0, "fchs">; +@@ -335,7 +335,7 @@ def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; + + // Versions of FP instructions that take a single memory operand. Added for the + // disassembler; remove as they are included with patterns elsewhere. +-let SchedRW = [WriteFComLd] in { ++let SchedRW = [WriteFComLd], Defs = [FPSW], Uses = [FPCW] in { + def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; + def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; + +@@ -398,22 +398,22 @@ defm CMOVNP : FPCMov<X86_COND_NP>; + + let Predicates = [HasCMov] in { + // These are not factored because there's no clean way to pass DA/DB. +-def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RST:$op), +- "fcmovb\t{$op, %st(0)|st(0), $op}">; +-def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RST:$op), +- "fcmovbe\t{$op, %st(0)|st(0), $op}">; +-def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RST:$op), +- "fcmove\t{$op, %st(0)|st(0), $op}">; +-def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RST:$op), +- "fcmovu\t{$op, %st(0)|st(0), $op}">; +-def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RST:$op), +- "fcmovnb\t{$op, %st(0)|st(0), $op}">; +-def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RST:$op), +- "fcmovnbe\t{$op, %st(0)|st(0), $op}">; +-def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RST:$op), +- "fcmovne\t{$op, %st(0)|st(0), $op}">; +-def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RST:$op), +- "fcmovnu\t{$op, %st(0)|st(0), $op}">; ++def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op), ++ "fcmovb\t{$op, %st|st, $op}">; ++def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RSTi:$op), ++ "fcmovbe\t{$op, %st|st, $op}">; ++def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RSTi:$op), ++ "fcmove\t{$op, %st|st, $op}">; ++def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RSTi:$op), ++ "fcmovu\t{$op, %st|st, $op}">; ++def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op), ++ "fcmovnb\t{$op, %st|st, $op}">; ++def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op), ++ "fcmovnbe\t{$op, %st|st, $op}">; ++def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op), ++ "fcmovne\t{$op, %st|st, $op}">; ++def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op), ++ "fcmovnu\t{$op, %st|st, $op}">; + } // Predicates = [HasCMov] + } // SchedRW + +@@ -454,7 +454,7 @@ def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$ + [(set RFP80:$dst, (X86fild addr:$src, i64))]>; + } // SchedRW + +-let SchedRW = [WriteStore] in { ++let SchedRW = [WriteStore], Uses = [FPCW] in { + def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, + [(store RFP32:$src, addr:$op)]>; + def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, +@@ -489,7 +489,7 @@ def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80 + def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>; + def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>; + } // mayStore +-} // SchedRW ++} // SchedRW, Uses = [FPCW] + + let mayLoad = 1, SchedRW = [WriteLoad] in { + def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">; +@@ -499,7 +499,7 @@ def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$ + def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">; + def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">; + } +-let mayStore = 1, SchedRW = [WriteStore] in { ++let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { + def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">; + def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">; + def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">; +@@ -513,7 +513,7 @@ def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$ + } + + // FISTTP requires SSE3 even though it's a FPStack op. +-let Predicates = [HasSSE3], SchedRW = [WriteStore] in { ++let Predicates = [HasSSE3], SchedRW = [WriteStore], Uses = [FPCW] in { + def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, + [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; + def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, +@@ -534,7 +534,7 @@ def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80 + [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; + } // Predicates = [HasSSE3] + +-let mayStore = 1, SchedRW = [WriteStore] in { ++let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { + def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">; + def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">; + def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">; +@@ -542,10 +542,10 @@ def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem: + + // FP Stack manipulation instructions. + let SchedRW = [WriteMove] in { +-def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op">; +-def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op">; +-def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op">; +-def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op">; ++def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">; ++def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">; ++def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">; ++def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">; + } + + // Floating point constant loads. +@@ -570,7 +570,7 @@ def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">; + let SchedRW = [WriteFLD1] in + def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">; + +-let SchedRW = [WriteFLDC], Defs = [FPSW] in { ++let SchedRW = [WriteFLDC] in { + def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>; + def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>; + def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>; +@@ -579,7 +579,7 @@ def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", + } // SchedRW + + // Floating point compares. +-let SchedRW = [WriteFCom] in { ++let SchedRW = [WriteFCom], Uses = [FPCW] in { + def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, + [(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>; + def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, +@@ -591,34 +591,37 @@ def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80 + + let SchedRW = [WriteFCom] in { + // CC = ST(0) cmp ST(i) +-let Defs = [EFLAGS, FPSW] in { +-def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, +- [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>; +-def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, +- [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>; ++let Defs = [EFLAGS, FPSW], Uses = [FPCW] in { ++def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, ++ [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>, ++ Requires<[FPStackf32, HasCMov]>; ++def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, ++ [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>, ++ Requires<[FPStackf64, HasCMov]>; + def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, +- [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; ++ [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>, ++ Requires<[HasCMov]>; + } + +-let Defs = [FPSW], Uses = [ST0] in { ++let Defs = [FPSW], Uses = [ST0, FPCW] in { + def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) +- (outs), (ins RST:$reg), "fucom\t$reg">; ++ (outs), (ins RSTi:$reg), "fucom\t$reg">; + def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop +- (outs), (ins RST:$reg), "fucomp\t$reg">; ++ (outs), (ins RSTi:$reg), "fucomp\t$reg">; + def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop + (outs), (ins), "fucompp">; + } + +-let Defs = [EFLAGS, FPSW], Uses = [ST0] in { ++let Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in { + def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) +- (outs), (ins RST:$reg), "fucomi\t$reg">; ++ (outs), (ins RSTi:$reg), "fucomi\t{$reg, %st|st, $reg}">; + def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop +- (outs), (ins RST:$reg), "fucompi\t$reg">; +-} ++ (outs), (ins RSTi:$reg), "fucompi\t{$reg, %st|st, $reg}">; + +-let Defs = [EFLAGS, FPSW] in { +-def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg), "fcomi\t$reg">; +-def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg), "fcompi\t$reg">; ++def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RSTi:$reg), ++ "fcomi\t{$reg, %st|st, $reg}">; ++def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg), ++ "fcompi\t{$reg, %st|st, $reg}">; + } + } // SchedRW + +@@ -628,12 +631,12 @@ let Defs = [AX], Uses = [FPSW] in + def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags + (outs), (ins), "fnstsw\t{%ax|ax}", + [(set AX, (X86fp_stsw FPSW))]>; +-let Defs = [FPSW] in ++let Defs = [FPSW], Uses = [FPCW] in + def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world + (outs), (ins i16mem:$dst), "fnstcw\t$dst", + [(X86fp_cwd_get16 addr:$dst)]>; + } // SchedRW +-let Defs = [FPSW], mayLoad = 1 in ++let Defs = [FPSW,FPCW], mayLoad = 1 in + def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] + (outs), (ins i16mem:$dst), "fldcw\t$dst", []>, + Sched<[WriteLoad]>; +@@ -642,8 +645,8 @@ def FLDCW16m : I<0xD9, MRM5m, // X8 + let SchedRW = [WriteMicrocoded] in { + let Defs = [FPSW] in { + def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>; +-def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg), "ffree\t$reg">; +-def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RST:$reg), "ffreep\t$reg">; ++def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">; ++def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">; + + // Clear exceptions + def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>; Index: patches/patch-lib_Target_X86_X86InstrInfo_td =================================================================== RCS file: patches/patch-lib_Target_X86_X86InstrInfo_td diff -N patches/patch-lib_Target_X86_X86InstrInfo_td --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-lib_Target_X86_X86InstrInfo_td 18 Feb 2019 19:05:40 -0000 @@ -0,0 +1,71 @@ +$OpenBSD$ + +Merge LLVM commits r340844, r353818 and r353819 from the 8.0 branch +to fix a regression in floating point operations. + +Index: lib/Target/X86/X86InstrInfo.td +--- lib/Target/X86/X86InstrInfo.td.orig ++++ lib/Target/X86/X86InstrInfo.td +@@ -3259,39 +3259,39 @@ def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; + // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with + // gas. + multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { +- def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"), +- (Inst RST:$op), EmitAlias>; +- def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"), ++ def : InstAlias<!strconcat(Mnemonic, "\t$op"), ++ (Inst RSTi:$op), EmitAlias>; ++ def : InstAlias<!strconcat(Mnemonic, "\t{%st, %st|st, st}"), + (Inst ST0), EmitAlias>; + } + +-defm : FpUnaryAlias<"fadd", ADD_FST0r>; ++defm : FpUnaryAlias<"fadd", ADD_FST0r, 0>; + defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; +-defm : FpUnaryAlias<"fsub", SUB_FST0r>; +-defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; +-defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; +-defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; +-defm : FpUnaryAlias<"fmul", MUL_FST0r>; +-defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; +-defm : FpUnaryAlias<"fdiv", DIV_FST0r>; +-defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; +-defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; +-defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; ++defm : FpUnaryAlias<"fsub", SUB_FST0r, 0>; ++defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0, 0>; ++defm : FpUnaryAlias<"fsubr", SUBR_FST0r, 0>; ++defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0, 0>; ++defm : FpUnaryAlias<"fmul", MUL_FST0r, 0>; ++defm : FpUnaryAlias<"fmulp", MUL_FPrST0, 0>; ++defm : FpUnaryAlias<"fdiv", DIV_FST0r, 0>; ++defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0, 0>; ++defm : FpUnaryAlias<"fdivr", DIVR_FST0r, 0>; ++defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0, 0>; + defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; + defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; +-defm : FpUnaryAlias<"fcompi", COM_FIPr>; +-defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; ++defm : FpUnaryAlias<"fcompi", COM_FIPr, 0>; ++defm : FpUnaryAlias<"fucompi", UCOM_FIPr, 0>; + + +-// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they ++// Handle "f{mulp,addp} $op, %st(0)" the same as "f{mulp,addp} $op", since they + // commute. We also allow fdiv[r]p/fsubrp even though they don't commute, + // solely because gas supports it. +-def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; +-def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; +-def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; +-def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; +-def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; +-def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; ++def : InstAlias<"faddp\t{$op, %st|st, $op}", (ADD_FPrST0 RSTi:$op), 0>; ++def : InstAlias<"fmulp\t{$op, %st|st, $op}", (MUL_FPrST0 RSTi:$op), 0>; ++def : InstAlias<"fsub{|r}p\t{$op, %st|st, $op}", (SUBR_FPrST0 RSTi:$op), 0>; ++def : InstAlias<"fsub{r|}p\t{$op, %st|st, $op}", (SUB_FPrST0 RSTi:$op), 0>; ++def : InstAlias<"fdiv{|r}p\t{$op, %st|st, $op}", (DIVR_FPrST0 RSTi:$op), 0>; ++def : InstAlias<"fdiv{r|}p\t{$op, %st|st, $op}", (DIV_FPrST0 RSTi:$op), 0>; + + def : InstAlias<"fnstsw" , (FNSTSW16r), 0>; + Index: patches/patch-lib_Target_X86_X86RegisterInfo_cpp =================================================================== RCS file: patches/patch-lib_Target_X86_X86RegisterInfo_cpp diff -N patches/patch-lib_Target_X86_X86RegisterInfo_cpp --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-lib_Target_X86_X86RegisterInfo_cpp 18 Feb 2019 19:07:16 -0000 @@ -0,0 +1,18 @@ +$OpenBSD$ + +Merge LLVM commits r340844, r353818 and r353819 from the 8.0 branch +to fix a regression in floating point operations. + +Index: lib/Target/X86/X86RegisterInfo.cpp +--- lib/Target/X86/X86RegisterInfo.cpp.orig ++++ lib/Target/X86/X86RegisterInfo.cpp +@@ -497,6 +497,9 @@ BitVector X86RegisterInfo::getReservedRegs(const Machi + BitVector Reserved(getNumRegs()); + const X86FrameLowering *TFI = getFrameLowering(MF); + ++ // Set the floating point control register as reserved. ++ Reserved.set(X86::FPCW); ++ + // Set the stack-pointer register and its aliases as reserved. + for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid(); + ++I) Index: patches/patch-lib_Target_X86_X86RegisterInfo_td =================================================================== RCS file: /home/cvs/ports/devel/llvm/patches/patch-lib_Target_X86_X86RegisterInfo_td,v retrieving revision 1.4 diff -u -p -u -p -r1.4 patch-lib_Target_X86_X86RegisterInfo_td --- patches/patch-lib_Target_X86_X86RegisterInfo_td 28 Jan 2019 06:27:28 -0000 1.4 +++ patches/patch-lib_Target_X86_X86RegisterInfo_td 18 Feb 2019 19:04:37 -0000 @@ -1,29 +1,53 @@ $OpenBSD: patch-lib_Target_X86_X86RegisterInfo_td,v 1.4 2019/01/28 06:27:28 jca Exp $ -The compiler is generally free to allocate general purpose registers in -whatever order it chooses. Reasons for choosing one register before another -usually include compiled instruction size (avoidance of REX prefixes, etc.) -or usage conventions, but somehow haven't included security implications in -the compiled bytecode. Some bytecode is more useful in polymorphic ROP -sequences than others, so it seems prudent to try to avoid that bytecode -when possible. +- The compiler is generally free to allocate general purpose registers in + whatever order it chooses. Reasons for choosing one register before another + usually include compiled instruction size (avoidance of REX prefixes, etc.) + or usage conventions, but somehow haven't included security implications in + the compiled bytecode. Some bytecode is more useful in polymorphic ROP + sequences than others, so it seems prudent to try to avoid that bytecode + when possible. -This patch moves EBX/RBX towards the end of the allocation preference for 32 -and 64 bit general purpose registers. Some instructions using RBX/EBX/BX/BL -as a destination register end up with a ModR/M byte of C3 or CB, which is often -useful in ROP gadgets. Because these gadgets often occur in the middle of -functions, they exhibit somewhat higher diversity than some other C3/CB -terminated gadgets. This change removes about 3% of total gadgets from the -kernel, but about 6% of unique gadgets. + This patch moves EBX/RBX towards the end of the allocation preference for 32 + and 64 bit general purpose registers. Some instructions using RBX/EBX/BX/BL + as a destination register end up with a ModR/M byte of C3 or CB, which is often + useful in ROP gadgets. Because these gadgets often occur in the middle of + functions, they exhibit somewhat higher diversity than some other C3/CB + terminated gadgets. This change removes about 3% of total gadgets from the + kernel, but about 6% of unique gadgets. -There are other possible changes in this direction. BX/BL are obvious next -targets for avoidance, and MM3/XMM3 may also be useful to try to avoid if -possible. + There are other possible changes in this direction. BX/BL are obvious next + targets for avoidance, and MM3/XMM3 may also be useful to try to avoid if + possible. +- Merge LLVM commits r340844, r353818 and r353819 from the 8.0 branch + to fix a regression in floating point operations. Index: lib/Target/X86/X86RegisterInfo.td --- lib/Target/X86/X86RegisterInfo.td.orig +++ lib/Target/X86/X86RegisterInfo.td -@@ -402,8 +402,8 @@ def GRH16 : RegisterClass<"X86", [i16], 16, +@@ -278,7 +278,7 @@ def K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, 100, 100]> + // pseudo registers, but we still mark them as aliasing FP registers. That + // way both kinds can be live without exceeding the stack depth. ST registers + // are only live around inline assembly. +-def ST0 : X86Reg<"st(0)", 0>, DwarfRegNum<[33, 12, 11]>; ++def ST0 : X86Reg<"st", 0>, DwarfRegNum<[33, 12, 11]>; + def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>; + def ST2 : X86Reg<"st(2)", 2>, DwarfRegNum<[35, 14, 13]>; + def ST3 : X86Reg<"st(3)", 3>, DwarfRegNum<[36, 15, 14]>; +@@ -288,8 +288,11 @@ def ST6 : X86Reg<"st(6)", 6>, DwarfRegNum<[39, 18, 17] + def ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]>; + + // Floating-point status word +-def FPSW : X86Reg<"fpsw", 0>; ++def FPSW : X86Reg<"fpsr", 0>; + ++// Floating-point control word ++def FPCW : X86Reg<"fpcr", 0>; ++ + // Status flags register. + // + // Note that some flags that are commonly thought of as part of the status +@@ -402,8 +405,8 @@ def GRH16 : RegisterClass<"X86", [i16], 16, R15WH)>; def GR32 : RegisterClass<"X86", [i32], 32, @@ -34,7 +58,7 @@ Index: lib/Target/X86/X86RegisterInfo.td // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since // RIP isn't really a register and it can't be used anywhere except in an -@@ -412,7 +412,7 @@ def GR32 : RegisterClass<"X86", [i32], 32, +@@ -412,7 +415,7 @@ def GR32 : RegisterClass<"X86", [i32], 32, // tests because of the inclusion of RIP in this register class. def GR64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, @@ -43,3 +67,13 @@ Index: lib/Target/X86/X86RegisterInfo.td // Segment registers for use by MOV instructions (and others) that have a // segment register as one operand. Always contain a 16-bit segment +@@ -521,6 +524,9 @@ def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32) + def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> { + let isAllocatable = 0; + } ++ ++// Helper to allow %st to print as %st(0) when its encoded in the instruction. ++def RSTi : RegisterOperand<RST, "printSTiRegOperand">; + + // Generic vector registers: VR64 and VR128. + // Ensure that float types are declared first - only float is legal on SSE1. Index: patches/patch-tools_clang_lib_Parse_ParseStmtAsm_cpp =================================================================== RCS file: patches/patch-tools_clang_lib_Parse_ParseStmtAsm_cpp diff -N patches/patch-tools_clang_lib_Parse_ParseStmtAsm_cpp --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-tools_clang_lib_Parse_ParseStmtAsm_cpp 18 Feb 2019 19:15:26 -0000 @@ -0,0 +1,17 @@ +$OpenBSD$ + +Merge LLVM commits r340844, r353818 and r353819 from the 8.0 branch +to fix a regression in floating point operations. + +Index: tools/clang/lib/Parse/ParseStmtAsm.cpp +--- tools/clang/lib/Parse/ParseStmtAsm.cpp.orig ++++ tools/clang/lib/Parse/ParseStmtAsm.cpp +@@ -637,7 +637,7 @@ StmtResult Parser::ParseMicrosoftAsmStatement(SourceLo + // Filter out "fpsw" and "mxcsr". They aren't valid GCC asm clobber + // constraints. Clang always adds fpsr to the clobber list anyway. + llvm::erase_if(Clobbers, [](const std::string &C) { +- return C == "fpsw" || C == "mxcsr"; ++ return C == "fpsr" || C == "mxcsr"; + }); + + // Build the vector of clobber StringRefs. Index: patches/patch-tools_lldb_source_Plugins_UnwindAssembly_x86_x86AssemblyInspectionEngine_cpp =================================================================== RCS file: patches/patch-tools_lldb_source_Plugins_UnwindAssembly_x86_x86AssemblyInspectionEngine_cpp diff -N patches/patch-tools_lldb_source_Plugins_UnwindAssembly_x86_x86AssemblyInspectionEngine_cpp --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-tools_lldb_source_Plugins_UnwindAssembly_x86_x86AssemblyInspectionEngine_cpp 18 Feb 2019 19:28:36 -0000 @@ -0,0 +1,34 @@ +$OpenBSD$ + +Skip retguard instructions in prologue detection. + +Index: tools/lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.cpp +--- tools/lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.cpp.orig ++++ tools/lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.cpp +@@ -593,6 +593,18 @@ bool x86AssemblyInspectionEngine::ret_pattern_p() { + return false; + } + ++// movq $0x????????(%rip), $reg [(0x4c || 0x48) 0x8b ?? ?? ?? ?? ??] ++// xorq $off(%rsp), $reg [(0x4c || 0x48) 0x33 ?? 0x24] ++bool x86AssemblyInspectionEngine::retguard_prologue_p(size_t offset, int insn_len) { ++ uint8_t *p = m_cur_insn; ++ if (offset == 0 && insn_len == 7) ++ return (*p == 0x48 || *p == 0x4c) && (*(p + 1) == 0x8b); ++ else if (offset == 7 && insn_len == 4) ++ return (*p == 0x48 || *p == 0x4c) && (*(p + 1) == 0x33) && (*(p + 3) == 0x24); ++ ++ return false; ++} ++ + uint32_t x86AssemblyInspectionEngine::extract_4(uint8_t *b) { + uint32_t v = 0; + for (int i = 3; i >= 0; i--) +@@ -1214,6 +1226,7 @@ bool x86AssemblyInspectionEngine::FindFirstNonPrologue + if (push_rbp_pattern_p() || mov_rsp_rbp_pattern_p() || + sub_rsp_pattern_p(scratch) || push_reg_p(regno) || + mov_reg_to_local_stack_frame_p(regno, scratch) || ++ retguard_prologue_p(offset, insn_len) || + (lea_rsp_pattern_p(scratch) && offset == 0)) { + offset += insn_len; + continue; Index: patches/patch-tools_lldb_source_Plugins_UnwindAssembly_x86_x86AssemblyInspectionEngine_h =================================================================== RCS file: patches/patch-tools_lldb_source_Plugins_UnwindAssembly_x86_x86AssemblyInspectionEngine_h diff -N patches/patch-tools_lldb_source_Plugins_UnwindAssembly_x86_x86AssemblyInspectionEngine_h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-tools_lldb_source_Plugins_UnwindAssembly_x86_x86AssemblyInspectionEngine_h 18 Feb 2019 19:28:52 -0000 @@ -0,0 +1,15 @@ +$OpenBSD$ + +Skip retguard instructions in prologue detection. + +Index: tools/lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.h +--- tools/lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.h.orig ++++ tools/lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.h +@@ -110,6 +110,7 @@ class x86AssemblyInspectionEngine { (private) + bool call_next_insn_pattern_p(); + bool mov_reg_to_local_stack_frame_p(int ®no, int &rbp_offset); + bool ret_pattern_p(); ++ bool retguard_prologue_p(size_t offset, int insn_len); + uint32_t extract_4(uint8_t *b); + + bool instruction_length(uint8_t *insn, int &length, uint32_t buffer_remaining_bytes); Index: patches/patch-utils_TableGen_X86RecognizableInstr_cpp =================================================================== RCS file: patches/patch-utils_TableGen_X86RecognizableInstr_cpp diff -N patches/patch-utils_TableGen_X86RecognizableInstr_cpp --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ patches/patch-utils_TableGen_X86RecognizableInstr_cpp 18 Feb 2019 19:13:28 -0000 @@ -0,0 +1,24 @@ +$OpenBSD$ + +Merge LLVM commits r340844, r353818 and r353819 from the 8.0 branch +to fix a regression in floating point operations. + +Index: utils/TableGen/X86RecognizableInstr.cpp +--- utils/TableGen/X86RecognizableInstr.cpp.orig ++++ utils/TableGen/X86RecognizableInstr.cpp +@@ -842,6 +842,7 @@ OperandType RecognizableInstr::typeFromString(const st + TYPE("f32mem", TYPE_M) + TYPE("ssmem", TYPE_M) + TYPE("RST", TYPE_ST) ++ TYPE("RSTi", TYPE_ST) + TYPE("i128mem", TYPE_M) + TYPE("i256mem", TYPE_M) + TYPE("i512mem", TYPE_M) +@@ -964,6 +965,7 @@ OperandEncoding + RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, + uint8_t OpSize) { + ENCODING("RST", ENCODING_FP) ++ ENCODING("RSTi", ENCODING_FP) + ENCODING("GR16", ENCODING_RM) + ENCODING("GR32", ENCODING_RM) + ENCODING("GR32orGR64", ENCODING_RM)