Currently only NHM architecture cpu model numbers are checked to
identify Intel cpus. This patch adds the Medfield model id to
this list. Medfield is based on Atom architecture. In Atom architecture
only the MSR_PKG_RESIDENCY registers need to be read and there is no
MSR_CORE_RESIDENCY or MSR_CPU_RESIDENCY registers. So only a new
nhm_package class needs to be created.
---
cpu/cpu.cpp | 1 +
cpu/intel_cpus.cpp | 10 ++++++++++
2 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/cpu/cpu.cpp b/cpu/cpu.cpp
index 2cc31ca..b901b87 100644
--- a/cpu/cpu.cpp
+++ b/cpu/cpu.cpp
@@ -68,6 +68,7 @@ static class abstract_cpu * new_package(int package, int cpu,
char * vendor, int
case 0x2F: /* Westmere-EX Xeon */
case 0x25: /* Westmere */
case 0x2C: /* Westmere */
+ case 0x27: /* Medfield Atom*/
ret = new class nhm_package;
break;
case 0x2A: /* SNB */
diff --git a/cpu/intel_cpus.cpp b/cpu/intel_cpus.cpp
index f42f3b4..db5afb2 100644
--- a/cpu/intel_cpus.cpp
+++ b/cpu/intel_cpus.cpp
@@ -60,6 +60,16 @@ static uint64_t get_msr(int cpu, uint64_t offset)
char msr_path[256];
fd = sprintf(msr_path, "/dev/cpu/%d/msr", cpu);
+
+ if (access(msr_path, R_OK) != 0){
+ fd = sprintf(msr_path, "/dev/msr%d", cpu);
+
+ if (access(msr_path, R_OK) != 0){
+ fprintf(stderr, "msr reg not found");
+ exit(-2);
+ }
+ }
+
fd = open(msr_path, O_RDONLY);
retval = pread(fd, &msr, sizeof msr, offset);
--
1.7.0.4
---------------------------------------------------------------------
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