Honestly Robert, I have no idea. This board has (2) processors, so the
only thing I can think of is maybe for security by having only (1)
usable nic? Your guess is as good as mine here. But, it is now working!
Thanks again!
On 2020-01-14 09:18, Robert ECEO Townley wrote:
On Mon, Jan 13, 2020 at 12:02 PM <jma...@42iso.com> wrote:
Morning all,
I actually sent this email last week, but I had attached some pictures and a BIOS file so it was in a pending state, and I just wanted to make sure I kept everyone up to date. That said I honestly do not know how many people actually receive this, but I wanted to at least update the group on the ever so slight remotely off chance that someone else happens upon this issue.
First, I want to thank Robert Townley and Michael Stumpf, who both lent a hand in this ordeal. It was eventually Michael who helped the most after we discovered that the schematics he had for the board were those for the 2nd generation XS23-TY3, and not the SX23-SB board that I had.
After some back and forth with Michael I ended up reaching out directly to SuperMicro, and after spending about 30 minutes with them trying to figure out where in the heck this guy came from, they got me over to a guy who has been there for quite some time and remember these guys. Thankfully he was able to get me the correct Owner's Manual and the last BIOS version that was released for this specific board.
During this whole process I had been through the BIOS settings several times, and was just flabbergasted at not being able to find literally any information anywhere about this issue. I had even looked all around the interfaces on the board for any type of pin grouping that might physically disable the port, but I didn't see anything that jumped out at me.
Though my initial plan was to access the console and see if there are any other settings there, which I still plan to do, I was at the point where I was going to jumper clear the CMOS, I just needed to find the pins. Now that I had the correct manual I found a nice diagram on page 1-4, and while I was looking for the CMOS clear pins, I noticed on page 1-5, under the quick reference guide was a very handy jumper reference, and wouldn't you believe it there on lines 2 and 3 were JPL1 and JPL2 for GLAN1 and GLAN2 with 'open' being the default and the ports enabled, with jumpered being disabled. Seeing as how I brought the first replacement board that I thought was "bad" with me to the office, I pulled it out to investigate.
Granted you almost need a microscope to read the writing, but sure enough right there between the South Bridge chip and DIMM A was a white jumper disabling JPL2 / GLAN2 / NIC2. See 'board_01.jpg' and 'board_02.jpg' attached to the email. I have not actually made it back to my rack to actually pull the server down and verify that this is the same issue, but I'm fairly confident that this was the culprit.
I still plan on accessing the serial console to see the options that are there, plus I am curious about the final firmware update to these boards. The last update was 1.2C, and I've actually attached that file on this email. It is X7DWT0.B19, and seeing as how I have a couple of these boards to spare, I'm going to go ahead and flash one of them using FlashRom [1] as SuperMicro said they no longer had access to the AMI flashing utility.
###UPDATE FROM 01/11/2020### I did make it to the environment this weekend, and sure enough the jumper was in place. I pulled it and when it powered back up she was lit up light a Christmas Tree. I did not get a chance to try the BIOS update as I didn't have the time I wanted to spend on it, and I sure didn't want to rush things.
When I do connect to the console and try the BIOS update, I'll update everyone again.
Again, thank you Robert and Michael for your help, and I hope everyone has a good evening.
-Jason
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[2].
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Awesome! Wondering why. A physical pin to disable a NIC in case there is
only one cpu?
Links:
------
[1] https://www.flashrom.org/Flashrom
[2]
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