Is there a way to determine the number of pins in a schematic? If so I will
write a macro to do this neat little guesstimate. It seems to work ok for
the tests I have done on digital ccts, probably a bit conservative for some
analogue ones I've tried it on.

-----Original Message-----
From: Mark Geddes [mailto:[EMAIL PROTECTED]]
Sent: Friday, 2 March 2001 6:00 AM
To: Multiple recipients of list ProtelEDAusers
Subject: RE: AW: [PROTEL EDA USERS]: Improv. PCB-Editor
(Density-Report?? ???)


Here is a density formula someone(?) sent me. I don't know how good it is,
and it definitely doesn't consider very many factors, but it might be of
interest to some forum members.

Mark Geddes

CALCULATING FOR BOARD DENSITY

1.      Count all pins to arrive at a total pin count.

2.      Calculate total board space in square inches.

3.      Use following formula:          Total pins / 16 = IC equivalents
                                        Board square inches / IC equivalents
= K

                                        K =  1.0 to .75         Then a 2
layer board is required
                                        K =  .75 to .50         Then a 4
layer board is required
                                        K =  .50 to .25         Then a 6
layer board is required
                                        K =  .25 to .18         Then a 8
layer board is required
                                        K =  .18 to .01         Then board
is very difficult
                                
                        Example 
                                        Total pin count 1600
                                        1600 / 16 =  100 
                                        IC Equivalents = 100
                                        Board is 5" x 6" =  30 sq in
                                        30 / 100 =  .30
                                        K = .30
                                        6 layer board is required

 
> The is a server add-on for P98 that calculates the manhattan 
> ratio which 
> is  density metric of some sort.  has not been 
> reworked/recompiled for 
> P99SE that I could see.  Though it couldn't be too hard to do 
> so if someone 
> so desired.
> 
> Also, George Messner covers density evaluations in moderate detail in 
> Section 1.5 of Printed Circuits Handbook 4th Edition. (Ed 
> Clyde F Coombs, 
> McGraw-Hill, ISBN 0-07-012754-9).  But this is possibly not 
> much use to you.
> 
> You can also get a density map (PCB:  Tools-Density Map) but 
> this is only 
> useful to show possible bottlenecks for routing after 
> placement.  It is not 
> useful for estimating degree of difficulty or possibility of success.
> 
> Advanced Route 3 had a pre-route phase where it estimated the 
> likelihood of 
> success based on number of nets, placement, routing 
> constraints etc.  But 
> this was also post-placement.
> 
> Some sort of industry standard (or at least 
> accepted/published) calculation 
> based only on number of connections, component footprints, 
> pad/via sizes 
> and routing technology (number of layers, blind/buried vias 
> etc) would be 
> possible.  The calculation could show the required routing 
> area given a 
> wiring efficiency factor Weff, (a number that is usually 
> about 50% but with 
> some blind/buried stack-ups may get close to 75%) or the 
> required Weff 
> given a board.  But I am not sure how useful this would be - 
> I have the 
> details for doing the calcs but I have never done them.
> 
> Something to toss about.  Maybe such analysis can be done 
> effectively these 
> days.
> 
> Ian Wilson
> 

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