See my post from 8 August re IBIS models. I have managed to use the IBIS converter on some of the devices designed here and can confirm that Protel does convert and load models correctly and seems to produce the sort of waveforms expected. The models I checked where from the IDT website and I used a simple input and output buffer and length of trace on a 4 layer stack up. I defined a 250 MHz clock and for the tracelength and impedance got what seemed to be 'correctly distorted' waveform for the board. See my other post in regards to setting it up. The SI rules have to be set up and the correct models defined for the components on the board, and I did also get warnings about this (which may be a bug) _______________________________________________________________ Clive Broome IDT Sydney Design Centre Ph: +61 2 9763 3513 8 Bayswater Dr, Homebush Fax: +61 2 9763 3409 Sydney, NSW, 2127 Email:[EMAIL PROTECTED] Australia Australia's Leading Semiconductor Designers --------------------------------------------------------------- "Colin Weber" <[EMAIL PROTECTED]> on 08/24/2001 03:23:16 PM Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> cc: (bcc: Clive Broome/sdc) Subject: Re: [PEDA] IBISTerry,
We just had a bloke leave us who had reviewed the Protel SI engine. Apparently
it isn't too bad (He actually thoroughly checked the results to make sure), and
he did get it to work. Unfortunately I don't know what he had to do to get it to work.
However, I do have some comments he made (I had to cut the figures to save size):
Signal slope requirements may be examined such as rise/fall time and flight time. The PCB layout may further be analysed by performing reflection or crosstalk
analysis on individual nets or group nets if any of the above tests fail. IBIS models may also be incorporated in a signal integrity simulation by using the IBIS translator provided by Protel.
You may specify as many requirements as you like such as min and max track impedance, max overshoot and min ad max signal slope. Before running a DRC check make
sure that you have specified the component types in preferences for correct signal integrity analysis . Likewise, specify the input stimulus and the supply nets. Then if you run the DRC
check and encounter errors you should go to the Tools menu and run the signal integrity tool.
this analysis refer to Protelís website: http://www.protel.com/earticles/index.html. Note that for components that are ICís, using the Edit buffer button along side with the IBIS translator,
you may specify the IBIS model (should vary for an input and output) for all ICís.
has been obtained, you may associate it with the IC using the Edit Buffer button.
The result of the simulation are as shown below:
Figure 6-1 shows the input stimulus and the crosstalk caused on a parallel net running from a transceiver to a receiver IC. The resultant crosstalk is then zoomed in and depicted in Figure 6-2. The blue graph
is the result of no terminaton on the 2 nets. The green graph is the result of termination but incorrect matching. The red graph is the result from proper termination.
At 04:59 AM 24/08/2001 +0100, you wrote:
On Thu, 23 Aug 2001 08:47:20 -0700, Brad Velander wrote:
I will just warn you on the SI6000 software, it is not cheap. I
>forget what the exact price was, I was expecting $800 - $1000USD. I gagged
>when I found the actual price, thousands, many thousands.
Their impedance tester is also far from cheap.
If you want other calculators you will find some at www.ultracad.com
The demo version of Hyperlynx at www.hyperlynx.com may also be useful but
I'm not sure how limited the current demo is.
Of course the signal integrity stuff in Protel should be able to do all
this and tell you which tracks you actually need to worry about, but, no
doubt is it buggy (the dialogs seemed to throw exceptions all the time when
I briefly played with it) and I don't suppose anyone figured out how to use
it, particularly how to set up models. Has anyone tried to use it? Has
anyone managed to import an IBIS model yet?
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