The right theme at the right time!

At the start of the week i was confronted with the same kind of problem.

The manufacturer of our multilayer-PCB send us the following statement:

"There are no clearances for some of the .0118 via holes on top and bottom
solder mask layers.
Plugging/Tenting both sides of the via holes is not recommended as air is
trapped in the via holes.  When the board encounters heat in subsequent
processes the air pressure increases and may lifts the soldermask around the
hole.  In order to avoid this problem we would to add .0065 dia. clearances
on top and bottom soldermask layers at where there are no clearances for the
via holes, unless otherwise notified. Note: these via will not be plugged or
tented.  Is this acceptable?"

I have allowed them to make the suggested changes.
But is it also possible, to tent only the top- OR the bottom-solder-mask
automatically?
In the "via-dialog" you can just select to tent the vias or not.
Do we need a "tent on top-solder" and "tent on bottom-solder" dialog?


Florian Finsterbusch

--------------------------------------------
Lightmaze AG
E-Mail: [EMAIL PROTECTED]


> -----Ursprungliche Nachricht-----
> Von: Harry Selfridge [mailto:[EMAIL PROTECTED]]
> Gesendet: Donnerstag, 13. September 2001 03:18
> An: Protel EDA Forum
> Betreff: Re: [PEDA] via tenting question
>
>
> "Tenting" is covering the pad and hole with solder mask.  "Plugging" the
> via is a much more expensive operation, and is not generally done unless
> one is worried about wicking solder away from joints such as BGA
> balls, or
> the via is plugged and surface plated to accommodate a spring loaded
> contact pin that might otherwise ream away the plating at the
> edge of the hole.
>
> Tenting has some small risk of chemical trapping, but most cleaning
> processes today are sufficient to reduce the risk to negligible.  I have
> been tenting vias with solder mask for over three decades and never had a
> failure that could be traced to trapped chemical contamination.  NASA /
> MILSPEC may have some limitation on tenting, but I am not familiar enough
> with those requirements to comment.
>
>
> At 06:10 PM 9/12/01 -0400, you wrote:
> >Hello, all:
> >
> >I am wondering what to do about vias.  I have a design for an
> 8-layer 0.090
> >in. PCB with about 700-800 vias 32mil pad, 18mil hole (no BGAs).
>  Since the
> >vias can be very close (6 mil) to other vias and pads, I want to
> cover the
> >vias with either soldermask or tent them.  What is the difference between
> >just covering them with soldermask, or tenting?  I guess tenting is where
> >the via holes are filled with an inert material to plug them, right?
> >
> >I have read in trade journals (such as PCB Design) that trapping residual
> >PCB etching chemicals inside vias can "eat them out" over time
> and result in
> >boards going bad after X years of service.  If this is so, wouldn't
> >soldermask AND tenting both trap these chemicals inside the via holes?
> >
> >Best regards,
> >Ivan Baggett
> >Bagotronix Inc.
> >website:  www.bagotronix.com
>

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