Hello,

I've been tasked to implement to state machine using a PLD (written in CUPL 
language) that will replace a "Phase Comparator 2" PLL. 

I have the State equations (from a PLL data sheet) and I know how to use an 
analog integration scheme to mimic a tristate output of the PLL chip using 
two State machine outputs.

I need to translation my state machine diagram into CUPL language. The protel 
help menus are not particularly helpful. Any guidance would be helpful.

Thanks in advance

Charlie Rich
Lightwave Electronics

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