Hello, I've been tasked to implement to state machine using a PLD (written in CUPL language) that will replace a "Phase Comparator 2" PLL.
I have the State equations (from a PLL data sheet) and I know how to use an analog integration scheme to mimic a tristate output of the PLL chip using two State machine outputs. I need to translation my state machine diagram into CUPL language. The protel help menus are not particularly helpful. Any guidance would be helpful. Thanks in advance Charlie Rich Lightwave Electronics * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
