Tim Fifield wrote: > > In 99SE PCB editor I wish to connect vias to the unused pins of a 100 pin > QFP for debug. When I run DRC it gives me short circuit and clearance > violations. Is there a way to create a net for each pin in PCB but not the > schematic editor so I won't get the violations? > > Tim Fifield
I show such testpoints on the schematic - I made a single pin symbol for the purpose, and a single pad PCB footprint to go with it. -- Peter Bennett TRIUMF 4004 Wesbrook Mall, Vancouver, BC, Canada GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
