At 13:13 22.11.01 -0400, you wrote: >In 99SE PCB editor I wish to connect vias to the unused pins of a 100 pin >QFP for debug. When I run DRC it gives me short circuit and clearance >violations. Is there a way to create a net for each pin in PCB but not the >schematic editor so I won't get the violations?
You can manually ad nets in the netlist manager and add them to the pads, but the Update PCB process will remove them again. I would add netlabels to the unused pins in Schematic, or even better create a schematic symbol and a pcb part for your testpoints (as I do). Then the schematic an the pcb is perfectly consistent. If you use the netlists instead of the syncronizer, check the box "include un-named single pin nets" in the netlist creation dialog. This should add nets to your unused pins, haven't tried this. Edi Im Hof >Tim Fifield ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + IH electronic + Phone: ++41 52 320 90 00 + + Edi Im Hof + Fax: ++41 52 320 90 04 + + Doernlerstrasse 1, Sulz + URL: http://www.ihe.ch + + CH-8544 Rickenbach-Attikon + E-Mail: [EMAIL PROTECTED] + + Switzerland + + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
