At 13:13 22.11.01 -0400, you wrote:
>In 99SE PCB editor I wish to connect vias to the unused pins of a 100 pin
>QFP for debug. When I run DRC it gives me short circuit and clearance
>violations. Is there a way to create a net for each pin in PCB but not the
>schematic editor so I won't get the violations?

You can manually ad nets in the netlist manager and add them to the pads, 
but the Update PCB process will remove them again.

I would add netlabels to the unused pins in Schematic, or even better 
create a schematic symbol and a pcb part for your testpoints (as I do). 
Then the schematic an the pcb is perfectly consistent.

If you use the netlists instead of the syncronizer, check the box "include 
un-named single pin nets" in the netlist creation dialog. This should add 
nets to your unused pins, haven't tried this.

Edi Im Hof


>Tim Fifield



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