hello out there,

i'm about to have my first PCB design involving controlled impedance traces 
manufactured in the near future (just a small run of protos).  I only have 
controlled impedance traces on the top layer.  using the transmission line 
impedance calculation tool at:

http://www.eskimo.com/~ultra/calc.htm

(which someone on this list pointed me to before, thanks!)

i've discovered that if I'm using FR4 and 7 mil traces with 2oz of copper, 
that a dielectric width of 6.3 mils will give me a reasonably close 
impedance (52.6 ohms and i'm aiming to get 50)

now here's my question - is this a reasonable way to do the layer stackup? 
(oh yeah, this is a 6 layer board and i'd like the resulting board to be 
.063" wide)

(TOP)
core -> 6.3 mils
prepreg -> 12.6 mils
core -> 12.6 mils
prepreg -> 12.6 mils
core ->  18.9 mils
(BOTTOM)

this seems logical to me but being as that i am inexperienced and such 
things and have noone knowledgeable around here to ask i thought i would 
ask for this group's wisdom.  thanks for any help, hope the 
non-directly-protel related question doesn't bother anyone.

-rimas


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