> Hi everybody, > > I have a question about the ground and power planes and signal layers that I must use on my printed circuit board. > > This board mainly consists of a virtex 2000 part ( FG1156 ball grid array,XCV2000E). > > I have followed the "xilinx board routability" guidelines and accordingly the board has six signal layers . > > But I don't know how many ground and power planes I will need ; > and where in the stack they should be placed with respect to the signal layers ?
This depends on whether you will be wanting controlled impedance traces, among lots of other things that the rest of the fellows will be able to explain better than I... > The board uses the following voltages : > > 3.3 Volts : LVTTL I/O's of the FPGA > 1.8 Volts : FPGA core voltage > 5.0 Volts : voltage required by other devices like the oscillator etc This comment is quite concerning to me.... Why are you using a 5.0V oscillator?? If the oscillator is for the FPGA I'd imagine that the FPGA won't have 5V tolerant clock inputs, and so would require a 3.3V oscillator. Best to check before doing the board design... > Will the presence of different voltages necessitate the use of different power planes for each voltage ? That depends on personal preference, how many devices draw power from that voltage rail and what kind of current they draw, as well as how far apart they are. Generally I'd go for the two largest voltages (in terms of current drawn by devices) and assign a plane to each of them. Then divide it up for the smaller (current draw) voltages. Have the ground planes as being continuous as much as possible, unless you have mixed signal designs, in which case divide in two one for digital and one for analog (possibly more depending on the speed of the digital). > Moreover, this board involves upto 544 (potentially) simultaneously switching signals ? That's alot of signals... If they're all synchronised to the same clock, this will cause problems (assuming the clock skew is equivalent for all parts). If you can possibly alter the clocking of the parts (ie change the time they switch) then voltage sag would be lessened. Otherwise you will need a very good supply decoupling scheme > Will this affect the ground and power planes ? In terms of voltage lost across the ground/power planes then it will indeed. In terms of EMI then again it will cause a great deal... if you can lag some of the clocks etc so that the switching is more distributed rather than all at once this would be reduced. > I'd really appreciate any suggestions... > > thanks and regards > > Anand Kulkarni * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
