I think that problems with copper imbalance are usually related to
imbalances within a layer, in turn providing a localized source for board
warpage. That is, 

Granted, etching problems can be associated with unbalanced copper on a
single layer, though more detail on your specific application would be
requiredto determine such a correspondence, and probably one you should
either know how to perform on your own or should be paying someone else to
execute...

Personally, in my own designs, if there is no reason to leave it out, I
would be more inclined to pour groundplane rather than to leave the areas
in-question open, since 
a) most of my design is low-frequency (<4MHz)
b) I am a believer in faraday shielding (3 dimensional enclosure of
signals), or as close to that ideal as possible.

Finally, the PCB house will like you "more betterer" if you deplete their
chemicals less than more...

IMO, unless there's a good reason to strip the board bare, (except for the
"only a few traces"), place a ground polygon (or several) on the layer to
gobble up that real-estate. You save energy, reduce polution, make the PCB
house happier, potentially get better etching, and add more shielding...

aj

> From: Michael Biggs [mailto:[EMAIL PROTECTED]]
> I have a 4-layer board top side components only. 
> The inner layers are spit-mixed power and ground
> plane, not necessarily in that order though. The
> bottom side of the board is almost bare with 
> only a few traces on it. My from anyone's 
> experience, is there a problem with bare board 
> mfg or the assembly mfg with this due to a 
> imbalance in copper distribution or anything?  

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