Ian,

I can state that it works for me - honest. The area of the PCB in question
is over 2 years old - obviously inherited from 99se.

In this case, the components in question are an array of LEDs with a light
pipe over them, all tightly
packed together.

I've not experimented with the actual parameters in DXP, but I know 'full
checking' MUST be on and I recall
having to play with the negative clearance in 99se, ending up at -127mm.

IIRC The online DRC always fails - annoyingly - but a full DRC passes with
this rule in place.

If I find time I'll take a look at it and see if I can work out *WHY* it
works.

It seems that this method perhaps does not work in all cases, at least
without some messing and plain luck.

I agree on the generalised clearance rule. Hm, perhaps this conversation
should be on DXP as it seems a little product enhancement is in order ;)

J.


-----Original Message-----
From: Ian Wilson [mailto:[EMAIL PROTECTED]
Sent: 09 July 2003 12:59
To: Protel EDA Forum
Cc: DXP Technical Forum
Subject: Re: [PEDA] adjacent component placement DXP


On 06:45 PM 9/07/2003, Jason Morgan said:
>Firstly you posted to the wrong list, this list is for Protel 99se, and not
>DXP,
>there is a separate list for DXP issues, see
>http://forums.altium.com/cgi-bin/msgbylist.asp?list=dxp

PEDA is not just for P99SE but is certainly mainly used for that - the 
Altium DXP list certainly has a much higher SNR both generally and for DXP 
related stuff.


>To answer your question, its the same as in 99se, you create a
>component-component clearance rule
>that uses the same component type for each side of the rule.
>
>I use this exact method for a mechanical part that sits over some LEDs.
>
>e.g.
>Create a rule in Placement: Component Clearance: New Rule
>HasFootprint('FOOTPRINT_1') vs HasFootprint('FOOTPRINT_1') you need to
>specify "Full Check"
>and a large negative clearance, e.g. -999mm

My experience is that this doesn't work.  DXP does not support negative 
clearance checking (overlaps).  It has been something I and others have 
been asking for for a while now.  I just tried a test case and couldn't get 
it to pass a batch DRC if I had any overlap at all - a negative clearance 
acted like a zero clearance.

Are you sure this has worked for you, Jason.  Can you give a little more 
detail? I would love to know why it doesn't work for me.

The only way I have been able to solve this sort of problem is by excluding 
the affected footprint from testing by making the general (All-All) rule 
into a:
NOT HasFootprint('FOOTPRINT_1') vs NOT HasFootprint('FOOTPRINT_1')

This excludes 'FOOTPRINT_1', in this case, from any clearance checking - 
but this then means that *no* component is checked against any component 
with footprint 'FOOTPRINT_1'.  I thought I had solved this issue to exclude 
just 'FOOTPRINT_1' from being checked against any other 'FOOTPRINT_1' but 
all other components being checked against each other and 'FOOTPRINT_1' but 
I can't recall and it is late.  I think there should be something in the 
DXP forum archive on this.

This solution is pretty poor as it doesn't scale well.  A number of users 
have been requesting generalised clearance rules (not just component and 
electrical) with negative clearance (overlap) capability.  Hopefully it 
will appear in a DXP SP soon.

Ian




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