At 01:11 PM 12/10/2003, Harry Selfridge wrote:
[an excellent discussion of signal noise, etc., particularly emphasizing what should be on every designers radar: return path.]


I might add that the rule that inexperienced engineers frequently use without thought - to connect analog and digital grounds at a single point - is often the worst thing to do. The single point ground only works if no significant signal current is going to pass through the common connection point, or the impedance of the single point is negligible. Forcing digital and analog returns through a common point results in modulation across the impedance of the single pad/via/pin.

I think this could be misunderstood. First of all, "single point ground" is a "rule" because it is, in fact, an appropriate solution in many circumstances. It fails as *rule* as do many rules when the reason for the rule is not understood and practice adjusted according to the immediate circumstances.


"Single point ground" is really a choice vs. "Multiple connection ground," not *isolated* ground. If you have a mixed analog/digital design with good physical isolation between the digital and analog sections, I'd expect that using a single ground plane, which is massively multiple, might work just fine, because return currents will flow within the sections. But if the physical layout does not allow that, controlling return currents so that they stay within their sections still is the appropriate practice, and, if the supplies are to be tied together, it may well be better to do it at one point than to do it at more than one point.

I first learned about single-point grounds in doing low-noise analog designs, not high-speed at all. Various subsystems would have their ground go back to a single point, typically the ground pin of the bulk power supply capacitance. This was always a fat pad, or sometimes a pad with a fat ring around it and multiple connections between the pad and ring (i.e., a thermal relief), with the various supply returns connecting around the ring.

High speed design is different because return currents attempt to track the signal physically across the board. If you have a ground plane close to a signal trace, the return current will be mostly confined to the plane immediately below the trace; any changes in the impedance of this pair may produce reflections, radiated noise, etc. When you move a signal from one layer to another with a via, the via may introduce a small impedance discontinuity, but, at the frequencies where I've worked, it can be neglected; however, what happens to the return current is not so easily set aside.

If the new layer is on the other side of the same ground plane, and the separation between the trace and the plane is the same on both sides, there will be little discontinuity. So one might, for example, have the layer on one side of the plane have traces in the X direction, and on the other side there will be traces in the Y direction; and one preferentially routes signals through this pair of layers to move around the board.

A stackup that I particularly like, if I want to keep layer count down to 6, is one with the power and ground layers in the middle, fairly close together. Then, on either side of them, symmetrically, are signal trace layers, X and Y as described. And above those signal layers are the top and bottom layers. To match impedance with the buried layers, traces on the top and bottom need to be relatively fat, because they are well above the reference planes.

There are a number of advantages to this stackup: the power and ground planes are close together (it might be 5 mils of prepreg or core between them). This creates a relatively high interplane capacitance which not only does yeoman work bypassing power -- perhaps even more effectively than scattered bypass caps -- but it also allows return currents to switch planes easily, through the interplane capacitance. Because the power and ground plane are so intimately connected at high frequency, they can act like a single plane for return purposes. The outside of the board serves to mount the parts and can be used for power traces or other low-speed signals, or, with the right trace widths, a few high-speed signals.

One common mistake I've seen with high-speed designs with split planes is to route signal traces across the plane splits. From the above discussion, that can be seen to be something to avoid, since the return current may have to detour far around the split to find its way home. It might even be better not to have a split plane than to do this.

I'll add that I'm not, strictly speaking, a design engineer and not a true expert on high-speed design; but I work with experts and some of it rubs off. I'll leave it to other with more specialized knowledge, on this list, to correct any errors....

Anyway, current always flows in a loop -- or else you'll build up a huge static charge! Many aspects of design, and particularly noise control, become simpler as we keep this in mind. With bypass caps, for example, the bypass cap stores charge and acts as a very short-term power supply for a chip which suddenly needs to pass a large current, as, for example, bipolar logic requires when switching. This current flows in a loop, and to minimize noise, the loop impedance should be minimized. A major factor in loop impedance is the area of the loop, the larger the area the larger the impedance. So how you route the power between the capacitor and the IC matters... but that is a whole other topic....





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