Richard
At 02:06 AM 1/14/2004, you wrote:
Hi,
Yesterday I started a new PCB design and I collided to this situation. Pleace see this file: http://groups.yahoo.com/group/protel-users/files/junk/PLANE_ERROR.jpg
This picture shows what is my problem. There is 3.3V plane and some PADs and VIA that are connected to it. The VIA seems OK to me, but what's wrong with the PADs?? There are relief to plane but there is also some kind of "opening" next to PADs that are connected to Plane.
Does anyone ever seen this (Iam NOT), how this can happen and how I can get rid of it?!
I have tried to assign net on LAyer Stack Manager, I tried to clear all nets -> reload it, I have checked all my Rules...
I also loaded my netlist to a new PCB file and it seems planeconnection to Plane is OK also for PADs.
Sincerely,
Juha Pajunen, Hw Engineer
Bitboys Oy
E-mail: [EMAIL PROTECTED]
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