Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 42eab40a12f12f044a5ca7b7d889d9a1f0d172ee
https://github.com/qemu/qemu/commit/42eab40a12f12f044a5ca7b7d889d9a1f0d172ee
Author: Peter Maydell <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Account for SME in aarch64_sve_narrow_vq() assertion
In aarch64_sve_narrow_vq() we assert that the new VQ is within
the maximum supported range for the CPU. We forgot to update
this to account for SME, which might have a different maximum.
Update the assert to permit any VQ which is valid for either
SVE or SME.
Cc: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 05f32d2584f40462aff5468cd47919b4a9077b9a
https://github.com/qemu/qemu/commit/05f32d2584f40462aff5468cd47919b4a9077b9a
Author: Peter Maydell <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M target/arm/gdbstub64.c
Log Message:
-----------
target/arm: Report correct vector width in gdbstub when SME present
Our gdbstub implementation of the org.gnu.gdb.aarch64.sve feature
doesn't account for SME correctly. We always report the Zn vector
registers with a width based on the maximum SVE vector register size,
even though SME's maximum size could be larger.
This is particularly bad in the case of a CPU with SME but not SVE,
because there the SVE vector width will be zero. If we report the Zn
registers in the XML as having a zero width then gdb falls over with
an internal error:
(gdb) target remote :1234
Remote debugging using :1234
/build/gdb-1WjiBe/gdb-15.0.50.20240403/gdb/aarch64-tdep.c:3066:
internal-error: aarch64_pseudo_register_type: bad register number 160
A problem internal to GDB has been detected,
further debugging may prove unreliable.
Report the Zn registers with their correct size. This matches how we
already handle the 'vg' pseudoregister in org.gnu.gdb.aarch64.sve: we
call sve_vqm1_for_el(), which returns the vector size accounting for
SME, not the pure SVE vector size.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Message-id: [email protected]
Commit: ee5bf0962ed6e0eb42d6bc9bfb3687f2408e3580
https://github.com/qemu/qemu/commit/ee5bf0962ed6e0eb42d6bc9bfb3687f2408e3580
Author: Peter Maydell <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Fix feature check in DO_SVE2_RRX, DO_SVE2_RRX_TB
In the macros DO_SVE2_RRX and DO_SVE2_RRX_TB we use the
feature check aa64_sve, thus exposing this set of instructions
in SVE as well as SVE2. Use aa64_sve2 instead, so they UNDEF
on an SVE1-only CPU as they should.
Strictly, the condition here should be "SVE2 or SME"; but we
will correct that in a following commit with all the other
missing "or SME" checks.
Cc: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Manos Pitsidianakis <[email protected]>
Message-id: [email protected]
Commit: 433097a2242120918090201129e5fbb8e16b3e34
https://github.com/qemu/qemu/commit/433097a2242120918090201129e5fbb8e16b3e34
Author: Peter Maydell <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm/tcg: Allow SVE RAX1 in SME2p1 streaming mode
The SVE RAX1 instruction is permitted in SME streaming mode starting
from SME2p1. We forgot to allow this relaxation when we implemented
SME2p1.
Cc: [email protected]
Fixes: 7b1613a1020d2 ("target/arm: Enable FEAT_SME2p1 on -cpu max")
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: aeb3c147fc4a1eb9a73f9f10923fc06def088aeb
https://github.com/qemu/qemu/commit/aeb3c147fc4a1eb9a73f9f10923fc06def088aeb
Author: Peter Maydell <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M docs/system/arm/cpu-features.rst
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Don't let 'sme=on' downgrade SME
In our handling of the boolean 'sme' CPU property, we write this 0/1
value directly to ID_AA64PFR1_EL1.SME. This worked when the only
valid values in that field were 0 (for no SME) and 1 (for SME1).
However, with the addition of SME2 the SME field can now also read 2.
This means that "-cpu max,sme=on" will result in an inconsistent set
of ID registers, where ID_AA64PFR1_EL1.SME claims SME1 but
ID_AA64SMFR0_EL1.SMEver claims SME2p1. This isn't a valid thing to
report, and confuses Linux into reporting SME2 to userspace but not
actually enabling userspace access for it.
Fix this bug by having arm_cpu_sme_finalize() fix up the
ID_AA64PFR1_EL1.SME field to match ID_AA64SMFR0.SMEver. This means
the "sme" property's semantics are "off" for "no SME" and "on" for
"enable at whatever the default SME version this CPU provides is".
Update the documentation to clarify what 'sve=on' and 'sme=on' do.
(We don't have the equivalent bug for 'sve=on' because
ID_AA64PFR0_EL1.SVE only has 0 and 1 as valid values, but the
semantics of the property are the same.)
Cc: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Manos Pitsidianakis <[email protected]>
Message-id: [email protected]
Commit: 8a21e4e27869b58a29e84437d0e8f0982cdbf50a
https://github.com/qemu/qemu/commit/8a21e4e27869b58a29e84437d0e8f0982cdbf50a
Author: Peter Maydell <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Handle SME-only CPUs in sve_vqm1_for_el_sm()
In sve_vqm1_for_el_sm(), we implicitly assume that the CPU has SVE:
if called with sm == false for non-streaming mode, we try to return a
vector length from svq_vq. This hits the "assert(sm)" at the bettom
of the function in an SME-only CPU where sve_vq.map is zero.
Add code to handle the "SME-only CPU not in streaming mode" case: we
report an effective VL of 128 bits, which is what the architecture
rule R_KXKNK says should be used when SVE instructions are disabled
or trapped but floating point instructions are enabled.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 5801dc1b3bc5c7b20d4cdc1d464d99e55d3eea3f
https://github.com/qemu/qemu/commit/5801dc1b3bc5c7b20d4cdc1d464d99e55d3eea3f
Author: Peter Maydell <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Handle SME-without-SVE on change of EL
aarch64_sve_change_el() currently assumes that SME implies
SVE, and will return without doing anything if SVE is not
implemented, skipping a possible requirement to change
the vector register state because the SME vector length
has changed. Update it to handle SME also.
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: e868257fe6887c26d635d3156aff8d41e1f4a879
https://github.com/qemu/qemu/commit/e868257fe6887c26d635d3156aff8d41e1f4a879
Author: Peter Maydell <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M target/arm/cpu-features.h
Log Message:
-----------
target/arm: Add aa64_sme_or_sve, aa64_sme_or_sve2 features
With FEAT_SME, even a CPU which does not implement FEAT_SVE is
allowed to execute the subset of SVE instructions which are permitted
in streaming SVE mode. We correctly handle this when the emulated
CPU has both FEAT_SVE and FEAT_SME, because sve_access_check()
includes the logic for this, matching the pseudocode
CheckSVEEnabled(). However if the emulated CPU only implement
FEAT_SME, it will fail the initial dc_isar_feature(aa64_sve, s)
feature check, because this doesn't match the check in the
per-instruction decode pseudocode, which is typically:
!IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME)
Add a new aa64_sme_or_sve feature function that we can use
to update the relevant uses of aa64_sve, and similarly
aa64_sme_or_sve2 for where we need to check FEAT_SVE2 || FEAT_SME.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: e69bddfc75bdc01f23786a26836bd351702507d7
https://github.com/qemu/qemu/commit/e69bddfc75bdc01f23786a26836bd351702507d7
Author: Peter Maydell <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm/tcg: Drop unnecessary aa64_sve check from do_trans_pmull()
Part of the logic inside do_trans_pmull() applies the aa64_sve
feature check for the non-128-bit-element versions of these insns
(PMULLB and PMULLT). This is currently a redundant check because we
only invoke this function via the macro invocation
TRANS_FEAT(..., aa64_sve2, do_trans_pmull, ...)
and it's actively wrong for an SME-only CPU, because these insns
are also available via SME. Remove the unnecessary logic.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 895d4367d6d8afca49c2d7ed6c9e95e853e72e7f
https://github.com/qemu/qemu/commit/895d4367d6d8afca49c2d7ed6c9e95e853e72e7f
Author: Peter Maydell <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm/tcg: Use "or SME" feature checks where needed
Many SVE instructions should be provided where the CPU implements
either SVE or SME. Currently we largely check only for features
aa64_sve or aa64_sve2. This happens to work because we forbid
creation of a CPU with SME but not SVE. To allow users to create
SME-only CPUs we need to update the conditions to use the "or SME"
versions of the feature tests instead.
This commit was created by going through translate-sve.c from
top to bottom looking for aa64_sve feature tests and cross
checking those against the instruction descriptions in the Arm ARM,
which will say "(FEAT_SVE || FEAT_SME)" for instructions that
are provided for both features, and "(FEAT_SME)" for the rarer
instructions that are SME only.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 5ca3420055d3c30a6a32ae8d0b03e2bf337734b2
https://github.com/qemu/qemu/commit/5ca3420055d3c30a6a32ae8d0b03e2bf337734b2
Author: Peter Maydell <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M target/arm/cpu-features.h
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm/tcg: Correct SVE/SME I8MM checks
The I8MM field of ID_AA64ZFR0_EL1 is set when the CPU implements
FEAT_I8MM and either FEAT_SVE or FEAT_SME. Currently we assume
that it is only set for FEAT_SVE. Update the feature checks:
* we rename the existing feature check function to sve_sme_i8mm
to indicate that it is true for either SVE or SME I8MM
* we add a new check function for FEAT_SVE && FEAT_I8MM (giving
it the sve_i8mm name that the old function used to have)
* the instructions which are (SVE || SME) && I8MM need their
checks updating to sve_sme_i8mm: these are SUDOT, USDOT
* instructions which are SVE && I8MM (i.e. really SVE-only) stay
unchanged with sve_i8mm: these are SMMLA, USMMLA, UMMLA
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 3c106377904f9aa08249696622c12df1ba5e7e66
https://github.com/qemu/qemu/commit/3c106377904f9aa08249696622c12df1ba5e7e66
Author: Peter Maydell <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M target/arm/cpu-features.h
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm/tcg: Correct SVE/SME BF16 checks
As with I8MM, the BF16 field of ID_AA64ZFR0_EL1 is set when the
CPU implements FEAT_BF16 and either FEAT_SVE or FEAT_SME, so
we need to have separate checks for "(SVE || SME) && BF16"
and "SVE && BF16". Follow the same pattern as with I8MM:
* aa64_sve_sme_bf16 means (SVE || SME) && BF16
* aa64_sve_bf16 means (SVE && BF16)
BFMMLA is the only SVE BF16 insn that isn't in SME.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 8952556536461af0b2fb398438275e19485943dc
https://github.com/qemu/qemu/commit/8952556536461af0b2fb398438275e19485943dc
Author: Peter Maydell <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M target/arm/cpu-features.h
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Don't squash all ID_AA64ZFR0_EL1 fields for non-SVE
The ID register ID_AA64ZFR0_EL1's fields are not all for SVE
exclusive features; some are also used to describe SME on an
SME-only CPU:
SVE-only fields:
* F64MM, F32MM, F16MM, SM4, B16B16, SVEVer
Fields used for SVE and SME (in some cases there is also a
field for SME in ID_AA64SMFR0_EL1, but it is just a "present
or absent" single bit flag and the ZFR0 field then tells you
what level of support is present):
* I8MM, SHA3, BF16, BitPerm, EltPerm, AES
Currently we zero the whole ID_AA64ZFR0_EL1 register in
arm_cpu_sve_finalize() if SVE is not present, which wipes also the
fields we need for SME. Only clear the fields which are SVE-specific
here, and clear the rest in arm_cpu_sme_finalize() if we
have neither SME nor SVE.
This requires us to update our ID_AA64ZFR0 field definitions
to match the rev M.a.a Arm ARM, as the F16MM SVE-only field
is not one we had a definition for previously.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: c38e9dc3b6e27e738f50920b02a8dd0c90a061ef
https://github.com/qemu/qemu/commit/c38e9dc3b6e27e738f50920b02a8dd0c90a061ef
Author: Peter Maydell <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Squash FEAT_SME_FA64 if FEAT_SVE is not present
FEAT_SME_FA64 allows Streaming SVE code to access the whole
SVE instruction set; it requires FEAT_SVE to be present. If
we have a CPU with SME but not SVE, squash the FA64 bit in
arm_cpu_sme_finalize().
This doesn't have any effect at the moment because we don't
let the user create an SME-without-SVE CPU, but we are about
to lift that restriction.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: a0660e2b2deb77725cc508ccc238619ca14edca8
https://github.com/qemu/qemu/commit/a0660e2b2deb77725cc508ccc238619ca14edca8
Author: Peter Maydell <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M docs/system/arm/cpu-features.rst
M target/arm/cpu.c
Log Message:
-----------
target/arm: Permit configurations with SME but not SVE
In commit f7767ca30179 ("target/arm: Disable SME if SVE is disabled")
we added code that forces SME to be disabled if SVE is disabled.
This was something we did in the run-up to a release to avoid an
assertion failure in smcr_write() if the user disabled SVE on the
'max' CPU without disabling SME also.
Now that we have corrected the code so that it doesn't assert
in an SME-without-SVE setup, we can let users select it.
This effectively reverts f7767ca30179.
Note that this now means that command lines like "-cpu max,sve=off"
which used to turn off SME and SVE will now give you a CPU with SME
but not SVE. This is permitted by our loose "max can always give you
extra stuff" rules, but may be unexpected to users. Mention this in
the CPU property documentation.
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Message-id: [email protected]
Commit: 1b33ed1689a1055e8c7c0faa91795b2a7e434e2e
https://github.com/qemu/qemu/commit/1b33ed1689a1055e8c7c0faa91795b2a7e434e2e
Author: BALATON Zoltan <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M hw/usb/hcd-ohci.c
Log Message:
-----------
hw/usb/hcd-ohci: Implement frame number overflow event
According to the USB OHCI specification section 6.5.6
("FrameNumberOverflow Event"), when bit 15 of the frame count changes
(either from 1 to 0 or 0 to 1) a FrameNumberOverflow interrupt should
be generated.
This fixes usb-audio on mac99,via=pmu with MacOS 9.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3274
Signed-off-by: BALATON Zoltan <[email protected]>
Tested-by: Elisey Konstantinov <[email protected]>
Message-id: [email protected]
[PMM: added brief comment, tweaked commit message]
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Commit: 4a22c50d4ab22f68f38e9c3e095ccceb9248bc15
https://github.com/qemu/qemu/commit/4a22c50d4ab22f68f38e9c3e095ccceb9248bc15
Author: Osama Abdelkader <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M target/arm/whpx/whpx-all.c
Log Message:
-----------
whpx: remove duplicate include
cpu.h is included twice
Signed-off-by: Osama Abdelkader <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 2755af839eeb57708353704bb51cc4ad9a3b9cbc
https://github.com/qemu/qemu/commit/2755af839eeb57708353704bb51cc4ad9a3b9cbc
Author: Osama Abdelkader <[email protected]>
Date: 2026-02-18 (Wed, 18 Feb 2026)
Changed paths:
M target/arm/whpx/whpx-all.c
Log Message:
-----------
whpx: fix FP register loop
In whpx_get_registers and whpx_set_registers the loops over FP registers
were using whpx_reg_match[i].reg instead of whpx_fpreg_match[i].reg
Signed-off-by: Osama Abdelkader <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Mohamed Mediouni <[email protected]
<mailto:[email protected]>>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 7bea97639e0505e911a639e8b7f12e2ddf2cabb0
https://github.com/qemu/qemu/commit/7bea97639e0505e911a639e8b7f12e2ddf2cabb0
Author: Peter Maydell <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M target/arm/debug_helper.c
A target/arm/tcg/debug.c
M target/arm/tcg/meson.build
Log Message:
-----------
target/arm: Move TCG-specific code out of debug_helper.c
The target/arm/debug_helper.c file has some code which we need
for non-TCG accelerators, but quite a lot which is guarded by
a CONFIG_TCG ifdef. Move all this TCG-only code out to a
new file target/arm/tcg/debug.c.
In particular all the code requiring access to the TCG
helper function prototypes is in the moved code, so we can
drop the use of tcg/helper.h from debug_helper.c.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: fefb9baf11959cfa8120507c06dc3670fe59f048
https://github.com/qemu/qemu/commit/fefb9baf11959cfa8120507c06dc3670fe59f048
Author: Peter Maydell <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Don't require helper prototypes in helper.c
In arm_cpu_do_interrupt_aarch64() we call the TCG helper function
helper_rebuild_hflags_a64(), which requires helper.c to include the
TCG helper function prototypes even when this file is being compiled
with TCG disabled.
We don't actually need to do this -- because we have already written
the new EL into pstate and updated env->aarch64, we can call
aarch64_rebuild_hflags() to achieve the same effect. This is the
function we use everywhere else in this file to update hflags.
Switch to aarch64_rebuild_hflags() and drop the include of the
TCG helper headers.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 7811dd39a6c131ad79bd0d15b5bc8ecd1dad9d0e
https://github.com/qemu/qemu/commit/7811dd39a6c131ad79bd0d15b5bc8ecd1dad9d0e
Author: Pierrick Bouvier <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
A target/arm/helper-mve.h
M target/arm/helper.h
A target/arm/tcg/helper-mve-defs.h
R target/arm/tcg/helper-mve.h
M target/arm/tcg/mve_helper.c
M target/arm/tcg/translate-mve.c
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: extract helper-mve.h from helper.h
A few points to mention:
- We mix helper prototypes and gen_helper definitions in a single header
for convenience and to avoid headers boilerplate.
- We rename existing tcg/helper-mve.h to helper-mve-defs.h to avoid
conflict when including helper-mve.h.
- We move mve helper_info definitions to tcg/mve_helper.c
We'll repeat the same for other helpers.
This allow to get rid of TARGET_AARCH64 in target/arm/helper.h.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 903a87216c150d63a4c44aedee015aceb42ecc18
https://github.com/qemu/qemu/commit/903a87216c150d63a4c44aedee015aceb42ecc18
Author: Pierrick Bouvier <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
A target/arm/helper-a64.h
M target/arm/helper.h
A target/arm/tcg/helper-a64-defs.h
M target/arm/tcg/helper-a64.c
R target/arm/tcg/helper-a64.h
M target/arm/tcg/mte_helper.c
M target/arm/tcg/pauth_helper.c
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: extract helper-a64.h from helper.h
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: af4ff26d4dbd35dc23f60d0a5c97cf044cc3ce34
https://github.com/qemu/qemu/commit/af4ff26d4dbd35dc23f60d0a5c97cf044cc3ce34
Author: Pierrick Bouvier <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
A target/arm/helper-sve.h
M target/arm/helper.h
M target/arm/tcg/gengvec64.c
A target/arm/tcg/helper-sve-defs.h
R target/arm/tcg/helper-sve.h
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-sme.c
M target/arm/tcg/translate-sve.c
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: extract helper-sve.h from helper.h
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 27031a759d1d29d55eb09006a79838f0b4390b27
https://github.com/qemu/qemu/commit/27031a759d1d29d55eb09006a79838f0b4390b27
Author: Pierrick Bouvier <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
A target/arm/helper-sme.h
M target/arm/helper.h
A target/arm/tcg/helper-sme-defs.h
R target/arm/tcg/helper-sme.h
M target/arm/tcg/sme_helper.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-sme.c
M target/arm/tcg/translate-sve.c
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: extract helper-sme.h from helper.h
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 9085154835063f13a9084eea7599f25ea5f5143f
https://github.com/qemu/qemu/commit/9085154835063f13a9084eea7599f25ea5f5143f
Author: Pierrick Bouvier <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M include/tcg/tcg.h
M tcg/tcg-internal.h
M tcg/tcg.c
Log Message:
-----------
tcg: move tcg_use_softmmu to tcg/tcg-internal.h
In next commit, we'll apply same helper pattern for base helpers
remaining.
Our new helper pattern always include helper-*-common.h, which ends up
including include/tcg/tcg.h, which contains one occurrence of
CONFIG_USER_ONLY.
Thus, common files not being duplicated between system and target
relying on helpers will fail to compile. Existing occurrences are:
- target/arm/tcg/arith_helper.c
- target/arm/tcg/crypto_helper.c
This occurrence of CONFIG_USER_ONLY is for defining variable
tcg_use_softmmu, and we rely on dead code elimination with it in various
tcg-target.c.inc.
Thus, move its definition to tcg/tcg-internal.h, so helpers can be
included by common files. Also, change it to a define, as it has fixed
values for now.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: bfc57f037d956f75607e678fb046581585ec319c
https://github.com/qemu/qemu/commit/bfc57f037d956f75607e678fb046581585ec319c
Author: Pierrick Bouvier <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M target/arm/helper.h
M target/arm/tcg/arith_helper.c
M target/arm/tcg/crypto_helper.c
M target/arm/tcg/debug.c
M target/arm/tcg/helper-a64.c
A target/arm/tcg/helper-defs.h
R target/arm/tcg/helper.h
M target/arm/tcg/hflags.c
M target/arm/tcg/m_helper.c
M target/arm/tcg/mte_helper.c
M target/arm/tcg/mve_helper.c
M target/arm/tcg/neon_helper.c
M target/arm/tcg/op_helper.c
M target/arm/tcg/pauth_helper.c
M target/arm/tcg/psci.c
M target/arm/tcg/sme_helper.c
M target/arm/tcg/sve_helper.c
M target/arm/tcg/tlb_helper.c
M target/arm/tcg/translate.c
M target/arm/tcg/translate.h
M target/arm/tcg/vec_helper.c
M target/arm/tcg/vfp_helper.c
Log Message:
-----------
target/arm: move exec/helper-* plumbery to helper.h
Since we cleaned helper.h, we can continue further and remove
all exec/helper-* inclusion. This way, all helpers use the same pattern,
and helper include details are limited to those headers.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 3580aa03547f92b658cabffbd13534e9f546c0bc
https://github.com/qemu/qemu/commit/3580aa03547f92b658cabffbd13534e9f546c0bc
Author: Pierrick Bouvier <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M target/arm/tcg/meson.build
M target/arm/tcg/psci.c
Log Message:
-----------
target/arm/tcg/psci.c: make compilation unit common
Now that helper.h does not contain TARGET_AARCH64 identifier, we can
move forward with this file.
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 3211199b00b9bbb78fe3da6b06c9126cab0368da
https://github.com/qemu/qemu/commit/3211199b00b9bbb78fe3da6b06c9126cab0368da
Author: Pierrick Bouvier <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M target/arm/tcg/meson.build
Log Message:
-----------
target/arm/tcg/cpu-v7m.c: make compilation unit common
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 4ba9234f67f296beb998b7d7f77d70722d5fd5c1
https://github.com/qemu/qemu/commit/4ba9234f67f296beb998b7d7f77d70722d5fd5c1
Author: Pierrick Bouvier <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M target/arm/tcg/meson.build
M target/arm/tcg/vec_helper.c
A target/arm/tcg/vec_helper64.c
M target/arm/tcg/vec_internal.h
Log Message:
-----------
target/arm/tcg/vec_helper.c: make compilation unit common
We need to extract 64 bits helper in a new file (vec_helper64.c), and
extract some macro definition also, since they will be used in both
files.
As well, DO_3OP_PAIR was defined twice, so rename the second variant
to DO_3OP_PAIR_NO_STATUS to reflect what it does.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 15500df3b3b05516eb80dddb4a9d29c0c28a02ab
https://github.com/qemu/qemu/commit/15500df3b3b05516eb80dddb4a9d29c0c28a02ab
Author: Pierrick Bouvier <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M target/arm/tcg/translate.h
Log Message:
-----------
target/arm/tcg/translate.h: replace target_ulong with vaddr
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 596081113bdd947ac8d8c85ba4a491df439c4d0d
https://github.com/qemu/qemu/commit/596081113bdd947ac8d8c85ba4a491df439c4d0d
Author: Pierrick Bouvier <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M target/arm/tcg/translate-a32.h
M target/arm/tcg/translate.c
M target/arm/tcg/translate.h
Log Message:
-----------
target/arm/tcg/translate.h: replace target_long with int64_t
target_long is used to represent a pc diff. Checked all call sites to
make sure we were already passing signed values, so extending works as
expected.
Use vaddr for pc_curr and pc_save.
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 10059583c7bfea50c1596310b0639669e93ce1ee
https://github.com/qemu/qemu/commit/10059583c7bfea50c1596310b0639669e93ce1ee
Author: Pierrick Bouvier <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M include/tcg/tcg-op-common.h
M include/tcg/tcg-op.h
M target/alpha/cpu-param.h
M target/alpha/translate.c
M target/arm/cpu-param.h
M target/avr/cpu-param.h
M target/avr/translate.c
M target/hexagon/cpu-param.h
M target/hexagon/translate.c
M target/hppa/cpu-param.h
M target/i386/cpu-param.h
M target/i386/tcg/translate.c
M target/loongarch/cpu-param.h
M target/loongarch/tcg/translate.c
M target/m68k/cpu-param.h
M target/m68k/translate.c
M target/microblaze/cpu-param.h
M target/microblaze/translate.c
M target/mips/cpu-param.h
M target/or1k/cpu-param.h
M target/or1k/translate.c
M target/ppc/cpu-param.h
M target/ppc/translate.c
M target/riscv/cpu-param.h
M target/rx/cpu-param.h
M target/rx/translate.c
M target/s390x/cpu-param.h
M target/sh4/cpu-param.h
M target/sh4/translate.c
M target/sparc/cpu-param.h
M target/sparc/translate.c
M target/tricore/cpu-param.h
M target/tricore/translate.c
M target/xtensa/cpu-param.h
M target/xtensa/translate.c
Log Message:
-----------
include/tcg/tcg-op.h: eradicate TARGET_INSN_START_EXTRA_WORDS
This commit removes TARGET_INSN_START_EXTRA_WORDS and force all arch to
call the same version of tcg_gen_insn_start, with additional 0 arguments
if needed. Since all arch have a single call site (in translate.c), this
is as good documentation as having a single define.
The notable exception is target/arm, which has two different translate
files for 32/64 bits. Since it's the only one, we accept to have two
call sites for this.
As well, we update parameter type to use uint64_t instead of
target_ulong, so it can be called from common code.
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 07f97d5da04a9f97e273de85c76f5017d8135a6e
https://github.com/qemu/qemu/commit/07f97d5da04a9f97e273de85c76f5017d8135a6e
Author: Peter Maydell <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M docs/system/arm/cpu-features.rst
M hw/usb/hcd-ohci.c
M include/tcg/tcg-op-common.h
M include/tcg/tcg-op.h
M include/tcg/tcg.h
M target/alpha/cpu-param.h
M target/alpha/translate.c
M target/arm/cpu-features.h
M target/arm/cpu-param.h
M target/arm/cpu.c
M target/arm/cpu64.c
M target/arm/debug_helper.c
M target/arm/gdbstub64.c
A target/arm/helper-a64.h
A target/arm/helper-mve.h
A target/arm/helper-sme.h
A target/arm/helper-sve.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/internals.h
M target/arm/tcg/arith_helper.c
M target/arm/tcg/crypto_helper.c
A target/arm/tcg/debug.c
M target/arm/tcg/gengvec64.c
A target/arm/tcg/helper-a64-defs.h
M target/arm/tcg/helper-a64.c
R target/arm/tcg/helper-a64.h
A target/arm/tcg/helper-defs.h
A target/arm/tcg/helper-mve-defs.h
R target/arm/tcg/helper-mve.h
A target/arm/tcg/helper-sme-defs.h
R target/arm/tcg/helper-sme.h
A target/arm/tcg/helper-sve-defs.h
R target/arm/tcg/helper-sve.h
R target/arm/tcg/helper.h
M target/arm/tcg/hflags.c
M target/arm/tcg/m_helper.c
M target/arm/tcg/meson.build
M target/arm/tcg/mte_helper.c
M target/arm/tcg/mve_helper.c
M target/arm/tcg/neon_helper.c
M target/arm/tcg/op_helper.c
M target/arm/tcg/pauth_helper.c
M target/arm/tcg/psci.c
M target/arm/tcg/sme_helper.c
M target/arm/tcg/sve_helper.c
M target/arm/tcg/tlb_helper.c
M target/arm/tcg/translate-a32.h
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-mve.c
M target/arm/tcg/translate-sme.c
M target/arm/tcg/translate-sve.c
M target/arm/tcg/translate.c
M target/arm/tcg/translate.h
M target/arm/tcg/vec_helper.c
A target/arm/tcg/vec_helper64.c
M target/arm/tcg/vec_internal.h
M target/arm/tcg/vfp_helper.c
M target/arm/whpx/whpx-all.c
M target/avr/cpu-param.h
M target/avr/translate.c
M target/hexagon/cpu-param.h
M target/hexagon/translate.c
M target/hppa/cpu-param.h
M target/i386/cpu-param.h
M target/i386/tcg/translate.c
M target/loongarch/cpu-param.h
M target/loongarch/tcg/translate.c
M target/m68k/cpu-param.h
M target/m68k/translate.c
M target/microblaze/cpu-param.h
M target/microblaze/translate.c
M target/mips/cpu-param.h
M target/or1k/cpu-param.h
M target/or1k/translate.c
M target/ppc/cpu-param.h
M target/ppc/translate.c
M target/riscv/cpu-param.h
M target/rx/cpu-param.h
M target/rx/translate.c
M target/s390x/cpu-param.h
M target/sh4/cpu-param.h
M target/sh4/translate.c
M target/sparc/cpu-param.h
M target/sparc/translate.c
M target/tricore/cpu-param.h
M target/tricore/translate.c
M target/xtensa/cpu-param.h
M target/xtensa/translate.c
M tcg/tcg-internal.h
M tcg/tcg.c
Log Message:
-----------
Merge tag 'pull-target-arm-20260219' of https://gitlab.com/pm215/qemu into
staging
target-arm queue:
* Allow TCG to emulate CPUs with SME but not SVE
* Refactorings for single-binary
* whpx: minor fixes
* hw/usb/hcd-ohci: Implement frame number overflow event
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# gpg: Signature made Thu Feb 19 10:31:52 2026 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [ultimate]
# gpg: aka "Peter Maydell <[email protected]>" [ultimate]
# gpg: aka "Peter Maydell <[email protected]>"
[ultimate]
# gpg: aka "Peter Maydell <[email protected]>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20260219' of https://gitlab.com/pm215/qemu: (32 commits)
include/tcg/tcg-op.h: eradicate TARGET_INSN_START_EXTRA_WORDS
target/arm/tcg/translate.h: replace target_long with int64_t
target/arm/tcg/translate.h: replace target_ulong with vaddr
target/arm/tcg/vec_helper.c: make compilation unit common
target/arm/tcg/cpu-v7m.c: make compilation unit common
target/arm/tcg/psci.c: make compilation unit common
target/arm: move exec/helper-* plumbery to helper.h
tcg: move tcg_use_softmmu to tcg/tcg-internal.h
target/arm: extract helper-sme.h from helper.h
target/arm: extract helper-sve.h from helper.h
target/arm: extract helper-a64.h from helper.h
target/arm: extract helper-mve.h from helper.h
target/arm: Don't require helper prototypes in helper.c
target/arm: Move TCG-specific code out of debug_helper.c
whpx: fix FP register loop
whpx: remove duplicate include
hw/usb/hcd-ohci: Implement frame number overflow event
target/arm: Permit configurations with SME but not SVE
target/arm: Squash FEAT_SME_FA64 if FEAT_SVE is not present
target/arm: Don't squash all ID_AA64ZFR0_EL1 fields for non-SVE
...
Signed-off-by: Peter Maydell <[email protected]>
Compare: https://github.com/qemu/qemu/compare/53af6529b1fe...07f97d5da04a
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