On 10/2/24 09:54, Michael Tokarev wrote:
09.02.2024 22:01, Philippe Mathieu-Daudé:
Replace '24' -> KVM_IOAPIC_NUM_PINS.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
hw/i386/kvm/ioapic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/kvm/ioapic.c b/hw/i386/kvm/ioapic.c
index 409d0c8c76..b96fe84eed 100644
--- a/hw/i386/kvm/ioapic.c
+++ b/hw/i386/kvm/ioapic.c
@@ -35,7 +35,7 @@ void kvm_pc_setup_irq_routing(bool pci_enabled)
kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
}
if (pci_enabled) {
- for (i = 0; i < 24; ++i) {
+ for (i = 0; i < KVM_IOAPIC_NUM_PINS; ++i) {
if (i == 0) {
kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, 2);
} else if (i != 2) {
There seems to be some confusion here about
KVM_IOAPIC_NUM_PINS vs IOAPIC_NUM_PINS (and
vs ICH9_LPC_IOAPIC_NUM_PINS).
Well this is what I'm trying to clear, isn't it?
KVM irqchip has a hard limit. ICH9_LPC_IOAPIC_NUM_PINS is
specified in the ICH9 datasheet. It is unclear to me what
IOAPIC_NUM_PINS represents, I suppose it emerged from the
evolution of the Frankenstein PC machine to Q35.
