Messages by Thread
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[PATCH] scripts/make-release: Go back to cloning all the EDK2 submodules
Peter Maydell
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[PATCH 0/2] target/arm: hvf: add timer freq note and stubbing LORC_EL1 reads
Mohamed Mediouni
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[PULL 0/1] tcg patch queue
Richard Henderson
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[PATCH] virtio: fix off-by-one and invalid access in virtqueue_ordered_fill
Jonah Palmer
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[PATCH 0/1] hw/arm: virt: add GICv2m for the case when ITS is not available
Mohamed Mediouni
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[PATCH] migration: show error message when postcopy fails
Daniel P . Berrangé
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[PULL 00/20] target-arm queue
Peter Maydell
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[PULL 10/20] target/arm: Add BFMIN, BFMAX (predicated)
Peter Maydell
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[PULL 05/20] host-utils: Drop workaround for buggy Apple Clang __builtin_subcll()
Peter Maydell
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[PULL 06/20] hw/misc/max78000_aes: Comment Internal Key Storage
Peter Maydell
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[PULL 12/20] target/arm: Add BFMLA, BFMLS (vectors)
Peter Maydell
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[PULL 01/20] hvf: arm: Remove $pc from trace_hvf_data_abort()
Peter Maydell
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[PULL 16/20] target/arm: Honour FPCR.AH=1 default NaN value in FMAXNMQV, FMINNMQV
Peter Maydell
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[PULL 08/20] target/arm: Add BFADD, BFSUB, BFMUL (unpredicated)
Peter Maydell
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[PULL 03/20] hw/misc/ivshmem-pci: Improve error handling
Peter Maydell
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[PULL 09/20] target/arm: Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM (predicated)
Peter Maydell
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[PULL 11/20] target/arm: Add BFMUL (indexed)
Peter Maydell
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[PULL 17/20] target/arm: Make LD1Q decode and trans fn agree about a->u
Peter Maydell
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[PULL 13/20] target/arm: Add BFMLA, BFMLS (indexed)
Peter Maydell
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[PULL 04/20] target/arm: Provide always-false kvm_arm_*_supported() stubs for usermode
Peter Maydell
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[PULL 07/20] docs: Fix Aspeed title
Peter Maydell
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[PULL 14/20] target/arm: Correct sense of FPCR.AH test for FMAXQV and FMINQV
Peter Maydell
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[PULL 19/20] hvf: arm: Emulate ICC_RPR_EL1 accesses properly
Peter Maydell
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[PULL 15/20] target/arm: Don't nest H() macro calls in SVE DO_REDUCE
Peter Maydell
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[PULL 20/20] accel/hvf: Display executable bit as 'X'
Peter Maydell
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[PULL 02/20] target/arm: Correct encoding of Debug Communications Channel registers
Peter Maydell
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Re: [PULL 02/20] target/arm: Correct encoding of Debug Communications Channel registers
Fabiano Rosas
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[PULL 18/20] hvf: arm: Add permission check in GIC sysreg handlers
Peter Maydell
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Re: [PULL 00/20] target-arm queue
Stefan Hajnoczi
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Re: apparent race condition in mttcg memory handling
Philippe Mathieu-Daudé
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[PATCH v6 00/24] migration: propagate vTPM errors using Error objects
Arun Menon
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[PATCH] rust: devices are not staticlibs
Paolo Bonzini
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[PULL v2 0/4] Misc crypto & UI patches
Daniel P . Berrangé
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Re: [PATCH] i386/kvm: Disable hypercall patching quirk by default
Mathias Krause
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Re: [PATCH] target/i386: Fix CR2 handling for non-canonical addresses
Mathias Krause
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KVM/QEMU community call for agenda items (22/7/25)
Alex Bennée
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GICv3 + GICv2m configuration for -M virt
Mohamed Mediouni
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Re: [PATCH-for-10.1] ui/curses: Fix infinite loop on windows
Philippe Mathieu-Daudé
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[PULL 0/5] Functional test patches and 32-bit arm Linux header removal
Thomas Huth
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[PATCH] hostmem/shm: Allow shm memory backend serve as shared memory for coco-VMs
Xiaoyao Li
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[PULL 00/12] Net patches
Jason Wang
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Re: [PATCH 00/50] ppc/xive: updates for PowerVM
Cédric Le Goater
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Galaxy S2 in QEMU
Hydra
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[PATCH v2 0/2] aarch64: update test images with new trusted firmware
Pierrick Bouvier
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[PULL 0/3] Display 20250718 patches
Gerd Hoffmann
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[RFC] target/arm: Concerns about mixed endian support for remote GDB
Vacha Bhavsar
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[PATCH for-10.1 00/10] target/arm: Some SVE2p1 fixes
Peter Maydell
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[PATCH for-10.1 01/10] target/arm: Add BFADD, BFSUB, BFMUL (unpredicated)
Peter Maydell
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Re: [PATCH for-10.1 01/10] target/arm: Add BFADD, BFSUB, BFMUL (unpredicated)
Richard Henderson
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[PATCH for-10.1 07/10] target/arm: Correct sense of FPCR.AH test for FMAXQV and FMINQV
Peter Maydell
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Re: [PATCH for-10.1 07/10] target/arm: Correct sense of FPCR.AH test for FMAXQV and FMINQV
Richard Henderson
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Re: [PATCH for-10.1 07/10] target/arm: Correct sense of FPCR.AH test for FMAXQV and FMINQV
Philippe Mathieu-Daudé
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[PATCH for-10.1 10/10] target/arm: Make LD1Q decode and trans fn agree about a->u
Peter Maydell
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Re: [PATCH for-10.1 10/10] target/arm: Make LD1Q decode and trans fn agree about a->u
Richard Henderson
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[PATCH for-10.1 03/10] target/arm: Add BFMIN, BFMAX (predicated)
Peter Maydell
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Re: [PATCH for-10.1 03/10] target/arm: Add BFMIN, BFMAX (predicated)
Richard Henderson
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[PATCH for-10.1 04/10] target/arm: Add BFMUL (indexed)
Peter Maydell
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Re: [PATCH for-10.1 04/10] target/arm: Add BFMUL (indexed)
Richard Henderson
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[PATCH for-10.1 09/10] target/arm: Honour FPCR.AH=1 default NaN value in FMAXNMQV, FMINNMQV
Peter Maydell
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Re: [PATCH for-10.1 09/10] target/arm: Honour FPCR.AH=1 default NaN value in FMAXNMQV, FMINNMQV
Richard Henderson
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[PATCH for-10.1 08/10] target/arm: Don't nest H() macro calls in SVE DO_REDUCE
Peter Maydell
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Re: [PATCH for-10.1 08/10] target/arm: Don't nest H() macro calls in SVE DO_REDUCE
Richard Henderson
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[PATCH for-10.1 06/10] target/arm: Add BFMLA, BFMLS (indexed)
Peter Maydell
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Re: [PATCH for-10.1 06/10] target/arm: Add BFMLA, BFMLS (indexed)
Richard Henderson
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[PATCH for-10.1 02/10] target/arm: Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM (predicated)
Peter Maydell
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Re: [PATCH for-10.1 02/10] target/arm: Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM (predicated)
Richard Henderson
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[PATCH for-10.1 05/10] target/arm: Add BFMLA, BFMLS (vectors)
Peter Maydell
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Re: [PATCH for-10.1 05/10] target/arm: Add BFMLA, BFMLS (vectors)
Richard Henderson
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[PATCH for-10.1] tcg/optimize: Don't fold INDEX_op_and_vec to extract
Richard Henderson
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[PATCH 0/4] hw: acpi: support SPCR rev. 3 & UART clock freq in ARM SPCR
Vadim Chichikalyuk