On Fri, 23 Feb 2024 at 20:53, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> On 2/23/24 00:32, Jinjie Ruan via wrote:
> > Add the NMIAR CPU interface registers which deal with acknowledging NMI.
> >
> > When introduce NMI interrupt, there are some updates to the semantics for
> > the
> > register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it
> > should return 1022 if the intid has super priority. And for ICC_NMIAR1_EL1
> > register, it should return 1023 if the intid do not have super priority.
> > Howerever, these are not necessary for ICC_HPPIR1_EL1 register.
> >
> > Signed-off-by: Jinjie Ruan <ruanjin...@huawei.com>
> > +static uint64_t icc_nmiar1_read(CPUARMState *env, const ARMCPRegInfo *ri)
> > +{
> > + GICv3CPUState *cs = icc_cs_from_env(env);
> > + uint64_t intid;
> > +
> > + if (icv_access(env, HCR_IMO)) {
> > + return icv_iar_read(env, ri);
> > + }
> > +
> > + if (!icc_hppi_can_preempt(cs)) {
> > + intid = INTID_SPURIOUS;
> > + } else {
> > + intid = icc_hppir1_value(cs, env, true, false);
>
> Here... believe that the result *should* only consider superpriority. I
> guess SPURIOUS is
> the correct result when there is no pending interrupt with superpriority?
> It's really
> unclear to me from the register description.
Should be 1023: the ICC_NMIAR1_EL1[] pseudocode in the GIC
architecture spec (13.1.8) does this:
if !IsNMI(intID) then
return ZeroExtend(INTID_SPURIOUS);
(Note that the logic is "find the highest priority
pending interrupt, and then see if it is an NMI or not",
not "find the highest priority pending NMI".)
-- PMM
