Sorry, manual is updated already and we do not notice that still.
https://www.loongson.cn/uploads/images/2023102309132647981.%E9%BE%99%E8%8A%AF%E6%9E%B6%E6%9E%84%E5%8F%82%E8%80%83%E6%89%8B%E5%86%8C%E5%8D%B7%E4%B8%80_r1p10.pdf
It is Chinese web link, English manual is not updated. Here is English
translation by manual with instruction "lddir rd, rj, level"
If the bit[14:13] of the register rj is not equal to 0 and its bit[6]
is 1, the value of the register rj is a marked as HugePage page entries.
In this case, the value from register rj is written directly to register rd.
If the bit[14:13] of the register rj is equal to 0 and its bit[6] is 1,
the value of the register rj is an Hugepage table entry. In this case,
replace the bit[14:13] of the register RJ value with level[1:0], the val
is written to the register rd.
If the bit[6] bit of register rj is 0, the value of the universal
register rj is the page table entry, it is physical address base page
table. In this case, if the LDDIR command is executed, the address will
be refilled according to the TLB currently processed. Retrieve the base
address of the next-level page table and write it to the common register
rd.
We will remove temporary lddir_ps, and record page size with bit[14:13]
in next version.
Regards
Bibo Mao
On 2024/3/6 下午12:10, Richard Henderson wrote:
On 3/5/24 17:52, lixianglai wrote:
The LDDIR_PS variable is not described in detail in the manual, but is
only an intermediate variable to assist in page size calculation
during tcg simulation.
This is exactly why I believe adding this intermediate variable is wrong.
What happens if LDPTE is *not* preceded by LDDIR? It's not the usual
way a tlb fill routine works, but *something* should happen if you
construct a valid huge page tlb entry by hand and pass it directly to
LDPTE.
With your implementation, this will not work because lddir_ps will not
be initialized. But I expect that on real hardware it would work.
If this does not work on real hardware, then there *is* some heretofore
undocumented hardware state. If so, then we need a description of this
state from the hardware engineers -- the documentation of LDDIR and
LDPTE need updating. Finally, this new hardware state needs to be added
to the migration state.
r~
