Currently only stage-2 translation is supported which is backed by shadow page table on host side. So we don't need exact matching of each bit of cap/ecap between vIOMMU and host. However, we can still ensure compatibility of host and vIOMMU's address width at least, i.e., vIOMMU's aw-bits <= host IOMMU aw-bits, which is missed before.
Signed-off-by: Yi Liu <yi.l....@intel.com> Signed-off-by: Zhenzhong Duan <zhenzhong.d...@intel.com> --- hw/i386/intel_iommu.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a49b587c73..d2cd186df0 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3824,6 +3824,21 @@ static int vtd_check_legacy_hdev(IntelIOMMUState *s, HostIOMMUDevice *hiod, Error **errp) { + HostIOMMUDeviceClass *hiodc = HOST_IOMMU_DEVICE_GET_CLASS(hiod); + HIOD_LEGACY_INFO info; + int ret; + + ret = hiodc->get_host_iommu_info(hiod, &info, sizeof(info), errp); + if (ret) { + return ret; + } + + if (s->aw_bits > info.aw_bits) { + error_setg(errp, "aw-bits %d > host aw-bits %d", + s->aw_bits, info.aw_bits); + return -EINVAL; + } + return 0; } -- 2.34.1