On 4/15/24 23:39, Chinmay Rath wrote:
The handler methods for divw[u] instructions internally use Rc(ctx->opcode),
for extraction of Rc field of instructions, which poses a problem if we move
the above said instructions to decodetree, as the ctx->opcode field is not
popluated in decodetree. Hence, making it decodetree compatible, so that the
mentioned insns can be safely move to decodetree specs.
Signed-off-by: Chinmay Rath<ra...@linux.ibm.com>
---
target/ppc/translate.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
+static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret,
+ TCGv arg1, TCGv arg2, bool sign,
+ bool compute_ov, bool compute_rc0)
Could drop the inline at the same time.
Let the compiler decide.
r~
