On 8/14/24 10:58, LIU Zhiwei wrote:
Thus if we want to use all registers of vectors, we have to add a dynamic constraint on register allocation based on IR types.
My comment vs patch 4 is that you can't do that, at least not without large changes to TCG.In addition, I said that the register pressure on vector regs is not high enough to justify such changes. There is, so far, little benefit in having more than 4 or 5 vector registers, much less 32. Thus 7 (lmul 4, omitting v0) is sufficient.
r~
