On Thu Dec 19, 2024 at 7:00 PM AEST, Akihiko Odaki wrote: > On 2024/12/18 16:42, Nicholas Piggin wrote: > > The e1000e and igb tests do not clear the ICR/EICR cause bits (or > > set auto-clear) on seeing queue interrupts, which inhibits the > > triggering of a new interrupt. > > > > Fix this by clearing the cause bits, and verify that the expected > > cause bit was set. > > > > Cc: Michael S. Tsirkin <m...@redhat.com> > > Cc: Marcel Apfelbaum <marcel.apfelb...@gmail.com> > > Cc: Dmitry Fleytman <dmitry.fleyt...@gmail.com> > > Cc: Akihiko Odaki <akihiko.od...@daynix.com> > > Cc: Sriram Yagnaraman <sriram.yagnara...@ericsson.com> > > Signed-off-by: Nicholas Piggin <npig...@gmail.com> > > --- > > tests/qtest/e1000e-test.c | 8 ++++++-- > > tests/qtest/igb-test.c | 8 ++++++-- > > 2 files changed, 12 insertions(+), 4 deletions(-) > > > > diff --git a/tests/qtest/e1000e-test.c b/tests/qtest/e1000e-test.c > > index de9738fdb74..a69759da70e 100644 > > --- a/tests/qtest/e1000e-test.c > > +++ b/tests/qtest/e1000e-test.c > > @@ -64,8 +64,10 @@ static void e1000e_send_verify(QE1000E *d, int > > *test_sockets, QGuestAllocator *a > > /* Put descriptor to the ring */ > > e1000e_tx_ring_push(d, &descr); > > > > - /* Wait for TX WB interrupt */ > > + /* Wait for TX WB interrupt (this clears the MSIX PBA) */ > > It doesn't clear the MSI-X PBA unless the next patch is applied. This > comment change should be moved to that patch.
Good catch. That was leftover from my improper PBA write patch. > > e1000e_wait_isr(d, E1000E_TX0_MSG_ID); > > + /* Read ICR which clears it ready for next interrupt, assert TXQ0 > > cause */ > > I suggest the following to make this comment clearer: > Read ICR to make it ready for next interrupt, assert TXQ0 cause Sure. Thanks, Nick
