Add CPUID enumeration for intel RDT monitoring and allocation, as well
as the flags used in the enumeration code.
Signed-off-by: Hendrik Wuethrich <whend...@google.com>
---
include/hw/i386/rdt.h | 23 +++++++++++++
target/i386/cpu.c | 75 +++++++++++++++++++++++++++++++++++++++++++
target/i386/cpu.h | 5 +++
3 files changed, 103 insertions(+)
diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h
index b63b433eef..a21bf804a6 100644
--- a/include/hw/i386/rdt.h
+++ b/include/hw/i386/rdt.h
@@ -29,8 +29,31 @@
#define RDT_MAX_L2_MASK_COUNT 63
#define RDT_MAX_MBA_THRTL_COUNT 63
+/* RDT L3 Cache Monitoring Technology */
+#define CPUID_F_0_EDX_L3 (1U << 1)
+#define CPUID_F_1_EDX_L3_OCCUPANCY (1U << 0)
+#define CPUID_F_1_EDX_L3_TOTAL_BW (1U << 1)
+#define CPUID_F_1_EDX_L3_LOCAL_BW (1U << 2)
+
+/* RDT Cache Allocation Technology */
+#define CPUID_10_0_EBX_L3_CAT (1U << 1)
+#define CPUID_10_0_EBX_L2_CAT (1U << 2)
+#define CPUID_10_0_EBX_MBA (1U << 3)
+
+/* RDT L3 Allocation features */
+#define CPUID_10_1_EAX_CBM_LENGTH 0xf
+#define CPUID_10_1_EBX_CBM 0x0
+#define CPUID_10_1_ECX_CDP 0x0 /* to enable, it would be (1U <<
2) */
#define CPUID_10_1_EDX_COS_MAX RDT_MAX_L3_MASK_COUNT
+
+/* RDT L2 Allocation features*/
+#define CPUID_10_2_EAX_CBM_LENGTH 0xf
+#define CPUID_10_2_EBX_CBM 0x0
#define CPUID_10_2_EDX_COS_MAX RDT_MAX_L2_MASK_COUNT
+
+/* RDT MBA features */
+#define CPUID_10_3_EAX_THRTL_MAX 89
+#define CPUID_10_3_ECX_LINEAR_RESPONSE (1U << 2)
#define CPUID_10_3_EDX_COS_MAX RDT_MAX_MBA_THRTL_COUNT
typedef struct RDTState RDTState;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 72ab147e85..cd06744451 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -42,6 +42,7 @@
#include "hw/boards.h"
#include "hw/i386/sgx-epc.h"
#endif
+#include "hw/i386/rdt.h"
#include "disas/capstone.h"
#include "cpu-internal.h"
@@ -6869,6 +6870,80 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
assert(!(*eax & ~0x1f));
*ebx &= 0xffff; /* The count doesn't need to be reliable. */
break;
+#ifndef CONFIG_USER_ONLY
+ case 0xF:
+ /* Shared Resource Monitoring Enumeration Leaf */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+#ifdef CONFIG_RDT
+ if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQM))
+ break;
+ if (!(cpu->rdtStatePerL3Cache)) {
+ warn_report("Intel RDT features enabled in commandline, "
+ "but rdt device not used");
+ break;
+ }
+ /* Non-zero count is ResId */
+ switch (count) {
+ /* Monitoring Resource Type Enumeration */
+ case 0:
+ *edx = env->features[FEAT_RDT_F_0_EDX];
+ *ebx = rdt_max_rmid(cpu->rdtStatePerL3Cache);
+ break;
+ case 1:
+ *ebx = 1;
+ *ecx = rdt_max_rmid(cpu->rdtStatePerL3Cache);
+ *edx = CPUID_F_1_EDX_L3_OCCUPANCY |
+ CPUID_F_1_EDX_L3_TOTAL_BW |
+ CPUID_F_1_EDX_L3_LOCAL_BW;
+ break;
+ }
+#endif
+ break;
+ case 0x10:
+ /* Shared Resource Director Technology Allocation Enumeration Leaf */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+#ifdef CONFIG_RDT
+ if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQE))
+ break;
+ if (!(cpu->rdtPerCore)) {
+ warn_report("Intel RDT features enabled in commandline, "
+ "but rdt device not used");
+ break;
+ }
+ /* Non-zero count is ResId */
+ switch (count) {
+ /* Cache Allocation Technology Available Resource Types */
+ case 0:
+ *ebx = CPUID_10_0_EBX_L3_CAT |
+ CPUID_10_0_EBX_L2_CAT |
+ CPUID_10_0_EBX_MBA;
+ break;
+ case 1:
+ *eax = CPUID_10_1_EAX_CBM_LENGTH;
+ *ebx = CPUID_10_1_EBX_CBM;
+ *ecx = CPUID_10_1_ECX_CDP;
+ *edx = CPUID_10_1_EDX_COS_MAX;
+ break;
+ case 2:
+ *eax = CPUID_10_2_EAX_CBM_LENGTH;
+ *ebx = CPUID_10_2_EBX_CBM;
+ *edx = CPUID_10_2_EDX_COS_MAX;
+ break;
+ case 3:
+ *eax = CPUID_10_3_EAX_THRTL_MAX;
+ *ecx = CPUID_10_3_ECX_LINEAR_RESPONSE;
+ *edx = CPUID_10_3_EDX_COS_MAX;
+ break;
+ }
+#endif
+ break;
+#endif
case 0x1C:
if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] &
CPUID_7_0_EDX_ARCH_LBR)) {
x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 08089ce6c2..6f5a3ecbd4 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -679,6 +679,7 @@ typedef enum FeatureWord {
FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */
FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */
FEAT_24_0_EBX, /* CPUID[EAX=0x24,ECX=0].EBX */
+ FEAT_RDT_F_0_EDX, /* CPUID[EAX=0xf,ECX=0].EDX (RDT CMT/MBM) */
FEATURE_WORDS,
} FeatureWord;
@@ -853,8 +854,12 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu,
FeatureWord w);
#define CPUID_7_0_EBX_RTM (1U << 11)
/* Zero out FPU CS and FPU DS */
#define CPUID_7_0_EBX_ZERO_FCS_FDS (1U << 13)
+/* Resource Director Technology Monitoring */
+#define CPUID_7_0_EBX_PQM (1U << 12)
/* Memory Protection Extension */
#define CPUID_7_0_EBX_MPX (1U << 14)
+/* Resource Director Technology Allocation */
+#define CPUID_7_0_EBX_PQE (1U << 15)
/* AVX-512 Foundation */
#define CPUID_7_0_EBX_AVX512F (1U << 16)
/* AVX-512 Doubleword & Quadword Instruction */
--
2.48.1.711.g2feabab25a-goog
