Implement rdmsr and wrmsr for the following MSRs:
* MSR_IA32_PQR_ASSOC
* MSR_IA32_QM_EVTSEL
* MSR_IA32_QM_CTR
* IA32_L3_QOS_Mask_n
* IA32_L2_QOS_Mask_n
* IA32_L2_QoS_Ext_BW_Thrtl_n
This allows for the guest to call RDT-internal functions to
associate an RMID with a CLOSID / set an active RMID for
monitoring, read monitoring data, and set classes of service.
Signed-off-by: Hendrik Wuethrich <whend...@google.com>
---
include/hw/i386/rdt.h | 4 ++
target/i386/cpu.h | 14 +++++
target/i386/tcg/system/misc_helper.c | 85 ++++++++++++++++++++++++++++
3 files changed, 103 insertions(+)
diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h
index d087627499..b63b433eef 100644
--- a/include/hw/i386/rdt.h
+++ b/include/hw/i386/rdt.h
@@ -29,6 +29,10 @@
#define RDT_MAX_L2_MASK_COUNT 63
#define RDT_MAX_MBA_THRTL_COUNT 63
+#define CPUID_10_1_EDX_COS_MAX RDT_MAX_L3_MASK_COUNT
+#define CPUID_10_2_EDX_COS_MAX RDT_MAX_L2_MASK_COUNT
+#define CPUID_10_3_EDX_COS_MAX RDT_MAX_MBA_THRTL_COUNT
+
typedef struct RDTState RDTState;
typedef struct RDTStatePerL3Cache RDTStatePerL3Cache;
typedef struct RDTStatePerCore RDTStatePerCore;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2cbcc8fe4e..08089ce6c2 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -577,6 +577,17 @@ typedef enum X86Seg {
#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
#define MSR_IA32_VMX_VMFUNC 0x00000491
+#define MSR_IA32_QM_EVTSEL 0x0c8d
+#define MSR_IA32_QM_CTR 0x0c8e
+#define MSR_IA32_PQR_ASSOC 0x0c8f
+
+#define MSR_IA32_L3_CBM_BASE 0x0c90
+#define MSR_IA32_L3_MASKS_END 0x0d0f
+#define MSR_IA32_L2_CBM_BASE 0x0d10
+#define MSR_IA32_L2_CBM_END 0x0d4f
+#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE 0xd50
+#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_END 0xd8f
+
#define MSR_APIC_START 0x00000800
#define MSR_APIC_END 0x000008ff
@@ -1883,6 +1894,9 @@ typedef struct CPUArchState {
uint64_t msr_ia32_feature_control;
uint64_t msr_ia32_sgxlepubkeyhash[4];
+ uint64_t msr_ia32_qm_evtsel;
+ uint64_t msr_ia32_pqr_assoc;
+
uint64_t msr_fixed_ctr_ctrl;
uint64_t msr_global_ctrl;
uint64_t msr_global_status;
diff --git a/target/i386/tcg/system/misc_helper.c
b/target/i386/tcg/system/misc_helper.c
index c9c4d42f84..7027f7228c 100644
--- a/target/i386/tcg/system/misc_helper.c
+++ b/target/i386/tcg/system/misc_helper.c
@@ -25,6 +25,7 @@
#include "exec/address-spaces.h"
#include "exec/exec-all.h"
#include "tcg/helper-tcg.h"
+#include "hw/i386/rdt.h"
#include "hw/i386/apic.h"
void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
@@ -293,6 +294,47 @@ void helper_wrmsr(CPUX86State *env)
env->msr_bndcfgs = val;
cpu_sync_bndcs_hflags(env);
break;
+#ifdef CONFIG_RDT
+ case MSR_IA32_QM_EVTSEL:
+ env->msr_ia32_qm_evtsel = val;
+ break;
+ case MSR_IA32_PQR_ASSOC:
+ env->msr_ia32_pqr_assoc = val;
+
+ if (!rdt_associate_rmid_cos(val))
+ goto error;
+ break;
+ case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE;
+
+ if (pos > CPUID_10_1_EDX_COS_MAX) {
+ goto error;
+ }
+ rdt_write_msr_l3_mask(pos, val);
+ break;
+ }
+ case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE;
+
+ if (pos > CPUID_10_2_EDX_COS_MAX) {
+ goto error;
+ }
+ rdt_write_msr_l2_mask(pos, val);
+ break;
+ }
+ case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ...
MSR_IA32_L2_QOS_Ext_BW_Thrtl_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] -
MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE;
+
+ if (pos > CPUID_10_3_EDX_COS_MAX) {
+ goto error;
+ }
+ rdt_write_mba_thrtl(pos, val);
+ break;
+ }
+#endif
case MSR_APIC_START ... MSR_APIC_END: {
int ret;
int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START;
@@ -471,6 +513,49 @@ void helper_rdmsr(CPUX86State *env)
val = cpu_x86_get_msr_core_thread_count(x86_cpu);
break;
}
+#ifdef CONFIG_RDT
+ case MSR_IA32_QM_CTR:
+ val = rdt_read_event_count(x86_cpu->rdtPerNode,
+ (env->msr_ia32_qm_evtsel >> 32) & 0xff,
+ env->msr_ia32_qm_evtsel & 0xff);
+ break;
+ case MSR_IA32_QM_EVTSEL:
+ val = env->msr_ia32_qm_evtsel;
+ break;
+ case MSR_IA32_PQR_ASSOC:
+ val = env->msr_ia32_pqr_assoc;
+ break;
+ case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE;
+
+ if (pos >= CPUID_10_1_EDX_COS_MAX) {
+ raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
+ }
+ val = rdt_read_l3_mask(pos);
+ break;
+ }
+ case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE;
+
+ if (pos >= CPUID_10_2_EDX_COS_MAX) {
+ raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
+ }
+ val = rdt_read_l2_mask(pos);
+ break;
+ }
+ case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ...
MSR_IA32_L2_QOS_Ext_BW_Thrtl_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] -
MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE;
+
+ if (pos >= CPUID_10_3_EDX_COS_MAX) {
+ raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
+ }
+ val = rdt_read_mba_thrtl(pos);
+ break;
+ }
+#endif
case MSR_APIC_START ... MSR_APIC_END: {
int ret;
int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START;
--
2.48.1.711.g2feabab25a-goog
