> -----Original Message-----
> From: Nicolin Chen <nicol...@nvidia.com>
> Sent: Wednesday, March 26, 2025 6:51 PM
> To: Eric Auger <eric.au...@redhat.com>
> Cc: Shameerali Kolothum Thodi
> <shameerali.kolothum.th...@huawei.com>; qemu-...@nongnu.org;
> qemu-devel@nongnu.org; peter.mayd...@linaro.org; j...@nvidia.com;
> ddut...@redhat.com; berra...@redhat.com; nath...@nvidia.com;
> mo...@nvidia.com; smost...@google.com; Linuxarm
> <linux...@huawei.com>; Wangzhou (B) <wangzh...@hisilicon.com>;
> jiangkunkun <jiangkun...@huawei.com>; Jonathan Cameron
> <jonathan.came...@huawei.com>; zhangfei....@linaro.org
> Subject: Re: [RFC PATCH v2 19/20] hw/arm/virt-acpi-build: Update IORT with
> multiple smmuv3-accel nodes
>
> > > for (i = 0; i < smmu_idmaps->len; i++) {
> > > + if (vms->iommu == VIRT_IOMMU_SMMUV3_ACCEL) {
> > > + offset = smmu_offset[i];
> > > + } else {
> > > + offset = smmu_offset[0];
>
> > maybe we can also use smmu_offset array for non accel mode and get rid
> > of this.
>
> I recall that my previous version does combine two modes, i.e.
> non-accel mode only uses smmu_offset[0]. Perhaps Shameer found some
> mismatch between smmu_idmaps->len and num_smmus?
Perhaps I did 😊. I think it was for a case where there were multiple host
bridges
associated with iommu=smmuv3. I will revisit to see this can be simplified.
Between, Thanks to both of you(and others of course!) for going through the
series.
I will consolidate the comments and rework the series soon.
Thanks,
Shameer
