On Tue, Apr 1, 2025 at 8:35 PM Jay Chang <jay.ch...@sifive.com> wrote:
>
> RISC-V AIA Spec states:
> "For a machine-level environment, extension Smaia encompasses all added
> CSRs and all modifications to interrupt response behavior that the AIA
> specifies for a hart, over all privilege levels. For a supervisor-level
> environment, extension Ssaia is essentially the same as Smaia except
> excluding the machine-level CSRs and behavior not directly visible to
> supervisor level."
>
> Since midelegh is an AIA machine-mode CSR, add Smaia extension check in
> aia_smode32 predicate.
>
> Reviewed-by: Frank Chang <frank.ch...@sifive.com>
> Signed-off-by: Jay Chang <jay.ch...@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 975d6e307f..81a57249bf 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -372,8 +372,11 @@ static RISCVException aia_smode(CPURISCVState *env, int
> csrno)
> static RISCVException aia_smode32(CPURISCVState *env, int csrno)
> {
> int ret;
> + int csr_priv = get_field(csrno, 0x300);
>
> - if (!riscv_cpu_cfg(env)->ext_ssaia) {
> + if (csr_priv == PRV_M && !riscv_cpu_cfg(env)->ext_smaia) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + } else if (!riscv_cpu_cfg(env)->ext_ssaia) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -5832,7 +5835,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MVIP] = { "mvip", aia_any, NULL, NULL, rmw_mvip },
>
> /* Machine-Level High-Half CSRs (AIA) */
> - [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
> + [CSR_MIDELEGH] = { "midelegh", aia_smode32, NULL, NULL, rmw_midelegh },
> [CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh },
> [CSR_MVIENH] = { "mvienh", aia_any32, NULL, NULL, rmw_mvienh },
> [CSR_MVIPH] = { "mviph", aia_any32, NULL, NULL, rmw_mviph },
> --
> 2.48.1
>
>
