On Tue, Apr 1, 2025 at 8:35 PM Jay Chang <jay.ch...@sifive.com> wrote:
>
> RISC-V Privileged Spec states:
> "In harts with S-mode, the medeleg and mideleg registers must exist, and
> setting a bit in medeleg or mideleg will delegate the corresponding trap
> , when occurring in S-mode or U-mode, to the S-mode trap handler. In
> harts without S-mode, the medeleg and mideleg registers should not
> exist."
>
> Add smode predicate to ensure these CSRs are only accessible when S-mode
> is supported.
>
> Reviewed-by: Frank Chang <frank.ch...@sifive.com>
> Signed-off-by: Jay Chang <jay.ch...@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 7948188356..975d6e307f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -5783,8 +5783,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> NULL, read_mstatus_i128 },
> [CSR_MISA] = { "misa", any, read_misa, write_misa,
> NULL, read_misa_i128 },
> - [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg },
> - [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg },
> + [CSR_MIDELEG] = { "mideleg", smode, NULL, NULL, rmw_mideleg
> },
> + [CSR_MEDELEG] = { "medeleg", smode, read_medeleg, write_medeleg
> },
> [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie },
> [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
> [CSR_MCOUNTEREN] = { "mcounteren", umode, read_mcounteren,
> @@ -5792,7 +5792,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>
> [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush,
> write_mstatush },
> - [CSR_MEDELEGH] = { "medelegh", any32, read_zero, write_ignore,
> + [CSR_MEDELEGH] = { "medelegh", smode32, read_zero, write_ignore,
> .min_priv_ver = PRIV_VERSION_1_13_0 },
> [CSR_HEDELEGH] = { "hedelegh", hmode32, read_hedelegh,
> write_hedelegh,
> .min_priv_ver = PRIV_VERSION_1_13_0 },
> --
> 2.48.1
>
>
