Re: [PATCH v2 10/12] target/riscv: rvv: Apply vext_check_input_eew to vector narrow instructions

[Daniel Henrique Barboza]

On 3/29/25 11:44 AM, Max Chou wrote:

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <ant...@tenstorrent.com>
Co-authored-by: Max Chou <max.c...@sifive.com>
Signed-off-by: Max Chou <max.c...@sifive.com>
---

With your co-authored-by tag removed:

Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>

  target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index f30157939b8..d4d1ad055fa 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -585,7 +585,8 @@ static bool vext_check_dds(DisasContext *s, int vd, int 
vs1, int vs2, int vm)

static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)

  {
-    bool ret = vext_narrow_check_common(s, vd, vs, vm);
+    bool ret = vext_narrow_check_common(s, vd, vs, vm) &&
+               vext_check_input_eew(s, vs, s->sew + 1, -1, 0, vm);
      if (vd != vs) {
          ret &= require_noover(vd, s->lmul, vs, s->lmul + 1);
      }
@@ -608,6 +609,7 @@ static bool vext_check_sd(DisasContext *s, int vd, int vs, 
int vm)
  static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm)
  {
      return vext_check_sd(s, vd, vs2, vm) &&
+           vext_check_input_eew(s, vs1, s->sew, vs2, s->sew + 1, vm) &&
             require_align(vs1, s->lmul);
  }