On 3/19/25 10:16, Pierrick Bouvier wrote:
If I understand correctly, this is simply an (arbitrary) choice related to each target
architecture implemented in QEMU, and it does not match any property of a *real* cpu. Is
that correct?
Correct.
In other words, it could have been implemented in a way that MMU_USER_IDX is the same for
all arch, but it hasn't been done this way. Is that correct?
I'm not looking for modifying anything related to this, just want to make sure I get it
right.
With minor effort, perhaps.
Take loongarch64 for example. The system register field CRMD.PVL contains the priv level,
where 0 is most priv and 3 is least. Simply extracting the field is the easiest
implementation, so MMU_USER_IDX == 3.
If there were some requirement that MMU_USER_IDX be 0, then obviously we could rearrange,
but so far there is not.
r~
