On Sun, May 11, 2025 at 11:18 PM Julian Ganz <neither@nut.email> wrote:
>
> We recently introduced API for registering callbacks for trap related
> events as well as the corresponding hook functions. Due to differences
> between architectures, the latter need to be called from target specific
> code.
>
> This change places hooks for RISC-V targets.
>
> Signed-off-by: Julian Ganz <neither@nut.email>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu_helper.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index d5039f69a9..dce7e34cba 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -36,6 +36,7 @@
> #include "cpu_bits.h"
> #include "debug.h"
> #include "pmp.h"
> +#include "qemu/plugin.h"
>
> int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
> {
> @@ -2173,6 +2174,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
> const bool prev_virt = env->virt_enabled;
> const target_ulong prev_priv = env->priv;
> + uint64_t last_pc = env->pc;
> target_ulong tval = 0;
> target_ulong tinst = 0;
> target_ulong htval = 0;
> @@ -2195,6 +2197,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> case RISCV_EXCP_SEMIHOST:
> do_common_semihosting(cs);
> env->pc += 4;
> + qemu_plugin_vcpu_hostcall_cb(cs, last_pc);
> return;
> #endif
> case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
> @@ -2464,6 +2467,12 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> prev_priv, prev_virt);
> }
>
> + if (async) {
> + qemu_plugin_vcpu_interrupt_cb(cs, last_pc);
> + } else {
> + qemu_plugin_vcpu_exception_cb(cs, last_pc);
> + }
> +
> /*
> * Interrupt/exception/trap delivery is asynchronous event and as per
> * zicfilp spec CPU should clear up the ELP state. No harm in clearing
> --
> 2.49.0
>
>
