On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
When pushing a context, any presented group interrupt should be redistributed before processing pending interrupts to present highest priority. This can occur when pushing the POOL ring when the valid PHYS ring has a group interrupt presented, because they share signal registers.
Reviewed-by: Michael Kowal<ko...@linux.ibm.com> Thanks, MAK
Signed-off-by: Nicholas Piggin <npig...@gmail.com> --- hw/intc/xive2.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 21cd07df68..392ac6077e 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -945,8 +945,9 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t nvp_blk, uint32_t nvp_idx, bool do_restore) { + uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); uint8_t *regs = &tctx->regs[ring]; - uint8_t ipb; + uint8_t ipb, nsr = sig_regs[TM_NSR]; Xive2Nvp nvp;/*@@ -978,6 +979,11 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, /* IPB bits in the backlog are merged with the TIMA IPB bits */ regs[TM_IPB] |= ipb;+ if (xive_nsr_indicates_group_exception(ring, nsr)) {+ /* redistribute precluded active grp interrupt */ + g_assert(ring == TM_QW2_HV_POOL); /* PHYS ring has the grp interrupt */ + xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, nsr)); + } xive2_tctx_process_pending(tctx, ring == TM_QW2_HV_POOL ? TM_QW3_HV_PHYS : ring); }
