On Wed, May 14, 2025 at 2:12 PM <frank.ch...@sifive.com> wrote:
>
> From: Frank Chang <frank.ch...@sifive.com>
>
> Add the missing implied rule for standard B extension.
> Standard B extension implies Zba, Zbb, Zbs extensions.
>
> RISC-V B spec: https://github.com/riscv/riscv-b
>
> Signed-off-by: Frank Chang <frank.ch...@sifive.com>
> Reviewed-by: Jerry Zhang Jian <jerry.zhangj...@sifive.com>
> Reviewed-by: Jim Shu <jim....@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 27edd5af62..f737b703da 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2532,6 +2532,17 @@ static RISCVCPUImpliedExtsRule RVG_IMPLIED = {
> },
> };
>
> +static RISCVCPUImpliedExtsRule RVB_IMPLIED = {
> + .is_misa = true,
> + .ext = RVB,
> + .implied_multi_exts = {
> + CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
> + CPU_CFG_OFFSET(ext_zbs),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {
> .ext = CPU_CFG_OFFSET(ext_zcb),
> .implied_multi_exts = {
> @@ -2910,7 +2921,8 @@ static RISCVCPUImpliedExtsRule SSCTR_IMPLIED = {
>
> RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
> &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
> - &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, NULL
> + &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED,
> + &RVB_IMPLIED, NULL
> };
>
> RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
> --
> 2.49.0
>
>
