Update aarch64-core.xml to include field definitions for PSTATE, which in gdb is modelled in the cpsr (current program status register) pseudo-register, named after the actual cpsr register in armv7.
Defining the fields layout of the register allows easy inspection of for example, the current exception level (EL): For example. Before booting a Linux guest, EL=2, but after booting and Ctrl-C'ing in gdb, we get EL=0: (gdb) info registers $cpsr cpsr 0x20402009 [ SP EL=2 BTYPE=0 PAN C ] (gdb) cont Continuing. ^C Thread 2 received signal SIGINT, Interrupt. 0x0000ffffaaff286c in ?? () (gdb) info registers $cpsr cpsr 0x20001000 [ EL=0 BTYPE=0 SSBS C ] The aarch64-core.xml has been updated to match exactly the version retrieved from upstream gdb, retrieved in 2025-05-19 from HEAD commit 9f4dc0b137c86f6ff2098cb1ab69442c69d6023d. https://sourceware.org/git/?p=binutils-gdb.git;a=tree;h=9f4dc0b137c86f6ff2098cb1ab69442c69d6023d Signed-off-by: Manos Pitsidianakis <manos.pitsidiana...@linaro.org> --- gdb-xml/aarch64-core.xml | 52 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 50 insertions(+), 2 deletions(-) diff --git a/gdb-xml/aarch64-core.xml b/gdb-xml/aarch64-core.xml index e1e9dc3f91370111eae36380449cddabc31265a4..b8046510b9a085d30463d37b3ecc8d435f5fb7a4 100644 --- a/gdb-xml/aarch64-core.xml +++ b/gdb-xml/aarch64-core.xml @@ -1,5 +1,5 @@ <?xml version="1.0"?> -<!-- Copyright (C) 2009-2012 Free Software Foundation, Inc. +<!-- Copyright (C) 2009-2025 Free Software Foundation, Inc. Contributed by ARM Ltd. Copying and distribution of this file, with or without modification, @@ -42,5 +42,53 @@ <reg name="sp" bitsize="64" type="data_ptr"/> <reg name="pc" bitsize="64" type="code_ptr"/> - <reg name="cpsr" bitsize="32"/> + + <flags id="cpsr_flags" size="4"> + <!-- Stack Pointer. --> + <field name="SP" start="0" end="0"/> + + <!-- Exception Level. --> + <field name="EL" start="2" end="3"/> + <!-- Execution state. --> + <field name="nRW" start="4" end="4"/> + + <!-- FIQ interrupt mask. --> + <field name="F" start="6" end="6"/> + <!-- IRQ interrupt mask. --> + <field name="I" start="7" end="7"/> + <!-- SError interrupt mask. --> + <field name="A" start="8" end="8"/> + <!-- Debug exception mask. --> + <field name="D" start="9" end="9"/> + + <!-- ARMv8.5-A: Branch Target Identification BTYPE. --> + <field name="BTYPE" start="10" end="11"/> + + <!-- ARMv8.0-A: Speculative Store Bypass. --> + <field name="SSBS" start="12" end="12"/> + + <!-- Illegal Execution state. --> + <field name="IL" start="20" end="20"/> + <!-- Software Step. --> + <field name="SS" start="21" end="21"/> + <!-- ARMv8.1-A: Privileged Access Never. --> + <field name="PAN" start="22" end="22"/> + <!-- ARMv8.2-A: User Access Override. --> + <field name="UAO" start="23" end="23"/> + <!-- ARMv8.4-A: Data Independent Timing. --> + <field name="DIT" start="24" end="24"/> + <!-- ARMv8.5-A: Tag Check Override. --> + <field name="TCO" start="25" end="25"/> + + <!-- Overflow Condition flag. --> + <field name="V" start="28" end="28"/> + <!-- Carry Condition flag. --> + <field name="C" start="29" end="29"/> + <!-- Zero Condition flag. --> + <field name="Z" start="30" end="30"/> + <!-- Negative Condition flag. --> + <field name="N" start="31" end="31"/> + </flags> + <reg name="cpsr" bitsize="32" type="cpsr_flags"/> + </feature> --- base-commit: 757a34115e7491744a63dfc3d291fd1de5297ee2 change-id: 20250519-gdbstub-aarch64-pstate-xml-d90bac349712 -- γαῖα πυρί μιχθήτω
