On 6/5/25 11:53 AM, Eric Auger wrote:
>
>
> On 6/2/25 5:41 PM, Shameer Kolothum wrote:
>> Although this change does not affect functionality at present, it is
>> required when we add support for user-creatable SMMUv3 devices in
>> future patches.
>>
>> Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
>> ---
>> hw/arm/smmuv3.c | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
>> index ab67972353..7e934336c2 100644
>> --- a/hw/arm/smmuv3.c
>> +++ b/hw/arm/smmuv3.c
>> @@ -24,6 +24,7 @@
>> #include "hw/qdev-properties.h"
>> #include "hw/qdev-core.h"
>> #include "hw/pci/pci.h"
>> +#include "hw/pci/pci_bridge.h"
>> #include "cpu.h"
>> #include "exec/target_page.h"
>> #include "trace.h"
>> @@ -1881,6 +1882,13 @@ static void smmu_realize(DeviceState *d, Error **errp)
>> SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
>> SysBusDevice *dev = SYS_BUS_DEVICE(d);
>> Error *local_err = NULL;
>> + Object *bus;
>> +
>> + bus = object_property_get_link(OBJECT(d), "primary-bus", &error_abort);
>> + if (!bus || !object_dynamic_cast(bus->parent, TYPE_PCI_HOST_BRIDGE)) {
>> + error_setg(errp, "SMMUv3 is not attached to any PCIe Root
>> Complex!");
>> + return;
>> + }
> shouldn't you check as well that !pci_bus_bypass_iommu(bus)?
I see you do the check in 6/6 and I think this is the correct way
because in case of legacy SMMU it is allowed to have
pci_bus_bypass_iommu set on the root bus to let the SMMU apply only on
pxb buses only. So please ignore this comment.
Eric
>
> Eric
>>
>> c->parent_realize(d, &local_err);
>> if (local_err) {
>
