I386 has already defined cache types in target/i386/cpu.h. Move CacheType to hw/core/cpu.h, so that ARM and other architectures could use it.
Cc: Alireza Sanaee <alireza.san...@huawei.com> Signed-off-by: Zhao Liu <zhao1....@intel.com> --- This is for Ali's ARM cache topology support: https://lore.kernel.org/qemu-devel/aefnfi+wglkml...@intel.com/ (Ali, if maintainer doesn't pick this, you can include this into your series freely.) --- include/hw/core/cpu.h | 6 ++++++ target/i386/cpu.h | 6 ------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1e87f7d393ec..33296a1c080e 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1126,4 +1126,10 @@ extern const VMStateDescription vmstate_cpu_common; #define UNASSIGNED_CPU_INDEX -1 #define UNASSIGNED_CLUSTER_INDEX -1 +enum CacheType { + DATA_CACHE, + INSTRUCTION_CACHE, + UNIFIED_CACHE +}; + #endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 1146465c8c62..8efea2ef2686 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1768,12 +1768,6 @@ typedef enum TPRAccess { /* Cache information data structures: */ -enum CacheType { - DATA_CACHE, - INSTRUCTION_CACHE, - UNIFIED_CACHE -}; - typedef struct CPUCacheInfo { enum CacheType type; uint8_t level; -- 2.34.1
