On 7/7/25 6:10 PM, Peter Maydell wrote:
> The GIC distributor registers GICD_TYPER2 is present when the
> GICv4.1 is implemented, and RES0 otherwise. QEMU's TCG implementation
> is only GICv4.0, so this register is RES0. However, since it's
> reasonable for GICv4.1-aware software to read the register, expecting
> the zero for GICv3 and GICv4.0, implement the case to avoid it being
> logged as an invalid guest read.
>
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Eric
> ---
> hw/intc/gicv3_internal.h | 1 +
> hw/intc/arm_gicv3_dist.c | 9 +++++++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
> index bc9f518fe86..fc586524f56 100644
> --- a/hw/intc/gicv3_internal.h
> +++ b/hw/intc/gicv3_internal.h
> @@ -31,6 +31,7 @@
> #define GICD_CTLR 0x0000
> #define GICD_TYPER 0x0004
> #define GICD_IIDR 0x0008
> +#define GICD_TYPER2 0x000C
> #define GICD_STATUSR 0x0010
> #define GICD_SETSPI_NSR 0x0040
> #define GICD_CLRSPI_NSR 0x0048
> diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
> index d8207acb22c..a7d10ed9493 100644
> --- a/hw/intc/arm_gicv3_dist.c
> +++ b/hw/intc/arm_gicv3_dist.c
> @@ -431,6 +431,15 @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
> (0xf << 19) | itlinesnumber;
> return true;
> }
> + case GICD_TYPER2:
> + /*
> + * This register only exists for GICv4.1, which QEMU doesn't
> + * currently emulate. On GICv3 and GICv4 it's defined to be RES0.
> + * We implement as read-zero here to avoid tracing a
> bad-register-read
> + * if GICv4.1-aware software reads this ID register.
> + */
> + *data = 0;
> + return true;
> case GICD_IIDR:
> /* We claim to be an ARM r0p0 with a zero ProductID.
> * This is the same as an r0p0 GIC-500.
